An analog multiplication circuit for outputting an output multiplied by an input electric current with a predetermined number can be provided with a simple structure. The circuit comprises a gate voltage control portion 1 having a first operation amplifier 13 and a first MOSFET 14 operated in a MOS Ohmic region and at least one operation portion 3 having the second operation amplifier 32, a first resistance 31, an electric current mirror circuit 34 and a second MOSFET 33 operated in a MOS Ohmic region, wherein a first input electric current I1 is supplied to the first MOSFET 14 and a second input electric current I2 is supplied to the first resistance 31 so as to output an output electric current IOUT by multiplying I1 with I2 from an output-side transistor 36 of the electric mirror circuit 34.