A semiconductor device manufacturing method that assures required size of flat areas at a wiring overlay nitride film, and forms an SAC structure wherein selectivity is not lowered at corners. A first etching process wherein an insulating film is etched under conditions for forming a vertical opening (vertical conditions) is used to open up the insulating film to a point near the wiring overlay nitride film 105. A second etching process is used wherein the insulating film is opened until the wiring overlay nitride film becomes exposed, by etching under conditions assuring a high ratio of selectivity relative to the wiring overlay nitride film (SAC conditions). Then, a third etching process is used wherein the insulating film located between first and second electrodes is removed by etching under conditions with a low ratio of selectivity relative to the wiring overlay nitride film (SAC conditions).

An insulating layer and a first silicon system layer are formed on a semiconductor substrate. An opening is formed in the first silicon system layer. A second silicon system layer is provided to cover the first silicon system layer and the opening. The second silicon system layer is etched to form a spacer on an inside wall of the opening so that the opening has a larger diameter at the top and a smaller diameter at the bottom. A protection layer is formed on the spacer; and the insulating layer is etched using the first silicon system layer, spacer and protection layer as a mask to form a contact hole therein.