A trenched field effect transistor is provided that includes (a) a semiconductor substrate, (b) a trench extending a predetermined depth into the semiconductor substrate, (c) a pair of doped source junctions, positioned on opposite sides of the trench, (d) a doped heavy body positioned adjacent each source junction on the opposite side of the source junction from the trench, the deepest portion of the heavy body extending less deeply into said semiconductor substrate than the predetermined depth of the trench, and (e) a doped well surrounding the heavy body beneath the heavy body.
A double-diffused metal-oxide-semiconductor ("DMOS") field-effect transistor (10) with a metal gate (26). A sacrificial gate layer is patterned to provide a self-aligned source mask. The source regions (20) are thus aligned to the gate (26), and the source diffusion provides a slight overlap (28) for good turn-on characteristics and low leakage. The sacrificial gate layer is capable of withstanding the diffusion temperatures of the DMOS process and is selectively etchable. After the high-temperature processing is completed, the sacrificial gate layer is stripped and a metal gate layer is formed over the substrate, filling the volume left by the stripped sacrificial gate material. In one embodiment, a chemical-mechanical polishing technique is used to planarize the metal gate layer.
A double-diffused metal-oxide-semiconductor ("DMOS") field-effect transistor (10) with a metal gate (26). A sacrificial gate layer is patterned to provide a self-aligned source mask. The source regions (20) are thus aligned to the gate (26), and the source diffusion provides a slight overlap (28) for good turn-on characteristics and low leakage. The sacrificial gate layer is capable of withstanding the diffusion temperatures of the DMOS process and is selectively etchable. After the high-temperature processing is completed, the sacrificial gate layer is stripped and a metal gate layer is formed over the substrate, filling the volume left by the stripped sacrificial gate material. In one embodiment, a chemical-mechanical polishing technique is used to planarize the metal gate layer.