A trenched semiconductor power device that includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. Each of the body regions extended between two adjacent trenched gates further having a gap exposing a top surface above an epitaxial layer above said semiconductor substrate. The trenched semiconductor power device further includes a Schottky junction barrier layer covering the top surface above the epitaxial layer between the trenched gate thus forming embedded Schottky diodes between adjacent trenched gates.
A method of manufacturing a semiconductor device having an active region and a termination region includes providing a semiconductor substrate having first and second main surfaces opposite to each other. The semiconductor substrate has an active region and a termination region surrounding the active region. The first main surface is oxidized. A first plurality of trenches and a first plurality of mesas are formed in the termination region. The first plurality of trenches in the termination region are filled with a dielectric material. A second plurality of trenches in the termination region. The second plurality of trenches are with the dielectric material.
A trenched semiconductor power device includes a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The trenched semiconductor power device further includes a first epitaxial layer above heavily doped substrate and beyond the trench bottom and a second epitaxial layer above said first epitaxial layer wherein a resistivity N1 of said first epitaxial layer is greater than a resistivity N2 of said second epitaxial layer represented by a functional relationship of N1>N2. In an exemplary embodiment, each of the trenched gates include an upper gate portion and lower gate portion formed with single polysilicon deposition processes wherein the lower gate portion is surrounded with a lower gate insulation layer having a greater thickness than an upper gate insulation layer surrounding the upper gate portion.
A method to manufacture a trenched semiconductor power device including a plurality of trenched gates surrounded by source regions near a top surface of a semiconductor substrate encompassed in body regions. The method for manufacturing the trenched semiconductor power device includes a step of carrying out a tilt-angle implantation through sidewalls of trenches to form drift regions surrounding the trenches at a lower portion of the body regions with higher doping concentration than the epi layer for Rds reduction, and preventing a degraded breakdown voltage due to a thick oxide in lower portion of trench sidewall and bottom. In an exemplary embodiment, the step of carrying out the tilt-angle implantation through the sidewalls of the trenches further includes a step of carrying out a tilt angle implantation with a tilt-angle ranging between 4 to 30 degrees.
A semiconductor power device includes a plurality of trenched gates. The trenched gates include a thin dielectric layer padded sidewalls of the trenched gate and a tub-shaped thick dielectric layer below a bottom of the trenched gates having a width narrower than the trenched gate. In an exemplary embodiment, the tub-shaped thick dielectric layer below a bottom of the trenched gates further includes a local deposition of silicon oxide (LOCOS) filling in a tub-shaped trench having a narrower width than the trenched gate. In another exemplary embodiment, the tub-shaped thick dielectric layer below a bottom of the trenched gates further comprising a high density plasma (HDP) chemical vapor deposition (CVD) silicon oxide filled in a tub-shaped trench having a narrower width than the trenched gate.