Provided is a receiver of a multi-input multi-output system using multiple antennas, the receiver including: a first multiplying unit for multiplying a vector r received via the antenna by a Hermitian matrix Q; a candidate transmitting vector generating unit for detecting a signal on a lowest modulation order transmitting antenna from the received vector y output from the first multiplying unit, creating as many symbol candidates as the modulation order of the detected signal, and generating a candidate transmitting vector using each symbol candidate; a transmitting vector determining unit for obtaining a distance between each candidate transmitting vector generated by the candidate transmitting vector generating unit and the received vector y to determine a final transmitting vector; and a demodulating unit for demodulating the final transmitting vector determined by the transmitting vector determining unit. Since the receiver detects a transmitting vector with reference to a signal on a lowest modulation order transmitting antenna, the receiver can have a simpler structure.
Provided is a transmitter for a multi-input multi-output system including: a memory for storing a modulation system and power allocation coefficient for each antenna; a modulating unit for modulating data to be transmitted using the modulation system for each antenna stored in the memory when the data to be transmitted is input; and a power adjusting unit for adjusting the power according to the power allocation coefficient for each antenna stored in the memory to transmit the data to be transmitted, modulated at the modulating unit, via a corresponding antenna. A higher performance gain can be provided compared to a conventional open loop V-BLAST system by using a different modulation system and power for each antenna of a transmitter.
A wireless modem is mounted to a terminal for wireless communication, and specifically controls an internal drive clock to reduce power consumption in an active mode. The wireless modem includes: a wireless core module for transmitting and receiving a radio signal; a modulator for converting data to be transmitted into a wireless transmission signal and transmitting the converted signal to the wireless core module; a demodulator for converting the signal received from the wireless core module into reception data; a synchronizer for synchronizing the signal received from the wireless core module; and a clock controller for generating a drive clock of each of the modulator, the demodulator, and the synchronizer. A low power clock controller is divided into six main functional blocks of a synchronizer, an analog controller, a modulator, a channel decoder, a demodulator, and a channel encoder, and has a feature that a clock is input only when a main functional block operates. As a result, it is possible to minimize power consumption caused by clock switching when an Orthogonal Frequency Division Multiplexing Access (OFDMA) mobile station modem operates in an active mode through the clock controller.
Provided are a multiplierless FIR digital filter and a method of designing the same, in which a filtering operation is performed by not multipliers needed as many as the number of tap depending on design requirement but a small addition/subtraction circuit using extracted information after analyzing the property of a given coefficient and extracting information required for design by only adding/subtracting operations. In the method of designing the multiplierless FIR digital filter, four tables are created to extract and store information needed for adding and subtracting operations to coefficients of design requirement, and an addition table is created to set a sixteen-multiple adding section of which a least upper bound is the maximum value of when the coefficient is represented into an integer by taking a decimal part of the coefficient, and to store values obtained by adding the input data input synchronizing with a clock frequency as a unit of sixteen sections. Further, a value corresponding to multiplication is obtained by performing extraction and error correction on the added values from four tables and the addition table, and an adder chain of an output terminal sums up the values and outputs the filtering results, thereby effectively implementing a logic circuit of the multiplierless FIR digital filter.
Provided is a method for converting a dimension of a vector. The vector dimension conversion method for vector quantization includes the steps of: extracting a specific parameter having a pitch period from an input speech signal and then generating a vector of a dimension that varies according to the pitch period; dividing an entire frequency domain of the generated vector of the variable dimension into at least two frequency domains; and converting the vector of the variable dimension into vectors of mutually different fixed dimensions according to the divided frequency domains. Thereby, not only an error due to the vector dimension conversion is suppressed but codebook memory required for the vector quantization is effectively reduced.