A high speed CMOS phase locked loop (PLL) (10) includes a three-state phase detection circuit having a frequency phase detector (12) coupled to a charge pump (14) for monitoring the phase differences between a reference frequency signal and a divided output frequency signal. The PLL can further include a loop filter (16)coupled to the three-state phase detection circuit, a VCO (18) coupled to the output of the loop filter, a VCO buffer (22) coupled to the output of the VCO for providing an output frequency signal, and a dual modulus prescaler (28) having a synchronous counter (27 and 29) using feedback among D flip-flops (30 and 32) for generating the divided output frequency signal.

An integrated circuit for wireless communications includes substrate, at least one integrated antenna formed in or on the substrate, and a heat sink. At least one dielectric propagating layer is disposed between the integrated antenna and the heat sink which provides a thermal conductivity of at least 35 W/m.multidot.K and resistivity greater than 100 Ohm-cm at 25 C. The invention can be used to establish an on-chip or inter-chip wireless link over at least a 2.2 cm distance.