A ring-style, multi-stage VCO of a phase lock loop circuit includes two or more differential amplifier stages. The phase lock loop includes a lowpass filter connected between a control voltage terminal and a voltage-to-current converter stage, which includes a first source-follower MOS transistor M1 with a source resistor R1 and a diode-connected MOS transistor M2 connected to its drain terminal. A current-source MOS transistor M8 has a gate terminal connected to the drain of the first MOS transistor M1 such that the transistor M8 mirrors current of transistor M1. A diode-connected transistor M9 has its gate terminal and its drain terminal connected together and also to the drain terminal of transistor M8. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN.sub.-- terminal. The drain terminal of MOS transistor M4 provides an OUT.sub.-- signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the drain terminal of transistor M9.

A ring-style, multi-stage VCO of a phase lock loop circuit includes two or more differential amplifier stages. The phase lock loop includes a lowpass filter connected between a control voltage terminal and a voltage-to-current converter stage, which includes a first source-follower MOS transistor M1 with a source resistor R1 and a second diode-connected MOS transistor M2 connected to its drain terminal. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN.sub.-- terminal. The drain terminal of MOS transistor M4 provides an OUT.sub.-- signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the voltage control input terminal of the phase lock loop.

An output buffer contains a totem-pole structure of four CMOS transistors. The top two are PMOS devices and the bottom two are NMOS devices. The top and bottom transistors function as output current switches which alternatively turn on and off the current flow from either VSS or VDD to the resistive termination load Rt. The middle two devices are connected to DC voltage references which control a precise amounts of current sourced to a load using a precision current source and sunk from a load using and to a precision current sink. The reference voltages for the precision current source and the current sink uses a negative feedback circuit which is referenced to a resistor ladder and a current source controlled by a band-gap reference source. This allows for on-chip referencing of ECL levels and control of reference voltages and currents in spite of variation is process, voltage, and temperature. Internal ECL reference levels signals V.sub.OL and V.sub.OH are used to control the output levels. Operational amplifiers drive the respective transistors such that voltage at the drains of the current source and sink transistors equals the ECL reference inputs VOH and VOL. These control voltages generate a precise currents through a replica stage and are also applied to the output stage. All of the devices in the reference control circuit are scaled to reduce DC power dissipation. For differential operation, a second totem-pole driver circuit is used with the inverse input data signal for controlling the output current switches.

A digital-to-analog (D/A) converter characterized by a decoder which decodes a multi-bit digital input into a plurality of cell activation signals; a converter comprising a number of current cells which can be individually activated by respective cell activation signals; a bias generator which develops a bias voltage for the current cells; and a compensator which compensates the bias voltage to reduce the effects of voltage variations in the power supply. The compensator includes a variation detector coupled to the power supply and develops an error signal when the power supply voltage fluctuates. A variation compensator is responsive to the error signal and is operative to stabilize the bias level. The method of the present invention includes the steps of developing a bias voltage from a power supply, sensing voltage variations in the power supply, and compensating the bias voltage to counteract the effects of the voltage variations.

A differential output buffer formed on a monolithic semiconductor substrate characterized by a bias generator coupled to a voltage source and a output stage coupled to the bias generator. The bias generator develops a bias output having a voltage level less than that of the voltage source. The output stage is responsive to a pair of complementary CMOS logic level inputs and uses the bias output of the bias generator to develop a pair of corresponding, low voltage swing outputs. In one embodiment the bias generator and the output stage operate in an open-loop and produce output signals which swing approximately two volts and in another embodiment the bias generator and the output stage operate in a closed-loop configuration and produce output signals which swing approximately one volt.