A semiconductor memory device capable of reducing power consumption by employing a DLL drive controller. The semiconductor memory device includes: an idle state detector for detecting an idle state that all banks are precharged; a delay locked loop (DLL) for synchronizing an internal clock with an external clock; and a DLL drive controller for controlling the delay locked loop in response to an idle state detection signal outputted from the idle state detector and a delay locked signal outputted from the DLL.
A semiconductor memory device capable of reducing power consumption by employing a DLL drive controller. The semiconductor memory device includes: an idle state detector for detecting an idle state that all banks are precharged; a delay locked loop (DLL) for synchronizing an internal clock with an external clock; and a DLL drive controller for controlling the delay locked loop in response to an idle state detection signal outputted from the idle state detector and a delay locked signal outputted from the DLL.
A semiconductor memory device having a register for stably generating an internal power supply voltage, including: a pumping circuit unit for generating the internal power supply voltage and adjusting a voltage level of the internal power supply voltage in response to a control signal; and a decoding unit for generating the control signal based on a plurality of address signals of the register.
Disclosed is a semiconductor memory device capable of reducing chip area by precharging all banks simultaneously. The semiconductor memory device includes: a command decoder for generating an auto refresh signal in response to an external command; an active information signal generator for generating an active information signal in response to a bank grouping signal when the auto refresh signal is activated; a tRAS controller for generating a tRAS control signal for each bank in response to an activated bank active detection signal, wherein the tRAS control signal maintains an active state during a row active time; a precharge information signal generator for generating a precharge information signal in response to the tRAS control signal of a last activated bank; and a bank control signal generator for generating a bank active signal in response to the active information signal and generates a bank precharge signal in response to the precharge information signal, respectively.
Disclosed is a semiconductor memory device capable of reducing chip area by precharging all banks simultaneously. The semiconductor memory device includes: a command decoder for generating an auto refresh signal in response to an external command; an active information signal generator for generating an active information signal in response to a bank grouping signal when the auto refresh signal is activated; a tRAS controller for generating a tRAS control signal for each bank in response to an activated bank active detection signal, wherein the tRAS control signal maintains an active state during a row active time; a precharge information signal generator for generating a precharge information signal in response to the tRAS control signal of a last activated bank; and a bank control signal generator for generating a bank active signal in response to the active information signal and generates a bank precharge signal in response to the precharge information signal, respectively.