A method for forming a dual damascene structure in a semiconductor device manufacturing process where via plugs which may include a thickness portion of a plug filling material overlying the process surface is formed by diffusing an acid into a plug filling material layer followed by reacting the acid with the plug filling material layer to form a soluble portion which is then removed using a solvent. A remaining portion of the plug filling material is cured and a BARC layer may be formed over the process surface prior to patterning trenches in an overlying resist layer and forming a dual damascene structure.
A matrix form semiconductor package substrate that has an electrode situated in-between a plurality of IC package substrates for providing electrical communication to conductive pads on the substrate is provided. The matrix form semiconductor package substrate includes a plurality of IC package substrates that are integrally formed on a strip in a matrix pattern that has a boundary between each two of the plurality of IC package substrates. Each of the plurality of IC package substrates has a multiplicity of conductive pad traces and an electrode, or a plating bar, formed in a serpentine configuration along the boundary for providing electrical communication to the multiplicity of conductive pads.
A method for reducing a critical dimension of a photoresist pattern while improving a line spacing between distal end portions of pattern lines wherein the method includes providing a substrate including an overlying resist; exposing the resist to an activating light source; baking the resist in a first baking process followed by developing the resist in a first development process to form a first resist pattern; then baking the first resist pattern in a second baking process followed by developing the first resist pattern in a second development process to form a second resist pattern having reduced dimensions; and, then dry trimming the second resist pattern to form a final resist pattern with reduced dimensions compared to the second resist pattern.
A semiconductor device having a semiconductor substrate and a first insulator overlying the semiconductor substrate. A spiral coil inductor overlies the first insulator and a second insulator overlies the spiral coil inductor. A patterned ferromagnetic film overlies the second insulator and a patterned magnetic-bias film overlies the patterned ferromagnetic film.
Novel dual damascene methods characterized by short cycle time and low expense. In one embodiment, the method includes providing a dielectric layer on a substrate; etching a via in the dielectric layer; filling the via with a conductive metal such as copper; providing a second dielectric layer over the via; etching a trench in the second dielectric layer; and filling the trench with a conductive metal such as copper. In another embodiment, the method includes providing a dielectric layer on a substrate; etching a partial via in the dielectric layer; etching a partial trench in the dielectric layer over the partial via; completing the via and the trench in a single etching step; and filling the via and the trench with a conductive metal such as copper to complete the via and metal line, respectively.