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| Patent # | Description |
|---|---|
| 2017/0133364 |
HIGH BREAKDOWN VOLTAGE III-N DEPLETION MODE MOS CAPACITORS III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to... |
| 2017/0133363 |
FET - BIPOLAR TRANSISTOR COMBINATION A transistor switch device is provided that exhibits relatively good voltage capability and relatively easy drive requirements to turn the device on and off.... |
| 2017/0133362 |
METHOD FOR PRODUCING TRENCH HIGH ELECTRON MOBILITY DEVICES A method for producing a solid state device, including forming a first dielectric layer over an epitaxial layer at least partially covering the a silicon... |
| 2017/0133361 |
COMPENSATED WELL ESD DIODES WITH REDUCED CAPACITANCE An integrated circuit with a shallow trench isolated, low capacitance, ESD protection diode. An integrated circuit with a gate space isolated, low capacitance,... |
| 2017/0133360 |
SEMICONDUCTOR DEVICE AND PROCESS OF MAKING THE SAME A semiconductor device includes a substrate, a seed layer, a first patterned metal layer, a dielectric layer and a second metal layer. The seed layer is... |
| 2017/0133359 |
SEMICONDUCTOR DEVICE WITH MODIFIED CURRENT DISTRIBUTION Semiconductor devices having modified current distribution and methods of forming the same are described herein. As an example, a memory die in contact with a... |
| 2017/0133358 |
Methods and systems to improve yield in multiple chips integration
processes The present disclosure includes systems and techniques relating to methods and systems that improve yield in multiple chips integration processes. In some... |
| 2017/0133357 |
DISPLAY DEVICE The embodiment provides a display device including an array substrate, an opposite substrate, a plurality of micro light-emitting diodes and a plurality of... |
| 2017/0133356 |
OPTOELECTRONIC DEVICE INCLUDING LIGHT-EMITTING DIODES AND A CONTROL
CIRCUIT An optoelectronic device including a first integrated circuit that includes: a substrate, having first and second opposite surfaces; and groups of sets of... |
| 2017/0133355 |
THREE-DIMENSIONAL PACKAGE STRUCTURE The present invention discloses a three-dimensional package structure. The first conductive element comprises a top surface, a bottom surface and a lateral... |
| 2017/0133354 |
INTEGRATED CIRCUIT PROCESS HAVING ALIGNMENT MARKS FOR UNDERFILL Packages having alignment marks and methods of forming the same are provided. A first workpiece is attached to a second workpiece. The first workpiece has an... |
| 2017/0133353 |
SEMICONDUCTOR ASSEMBLY WITH THREE DIMENSIONAL INTEGRATION AND METHOD OF
MAKING THE SAME A semiconductor assembly includes a face-to-face semiconductor sub-assembly electrically coupled to a circuit board by bonding wires. The face-to-face... |
| 2017/0133352 |
THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH THREE DIMENSIONAL
INTEGRATION AND METHOD OF MAKING THE SAME A semiconductor assembly with three dimensional integration includes a face-to-face semiconductor sub-assembly electrically coupled to a heat spreader by... |
| 2017/0133351 |
Multi-Stack Package-on-Package Structures A package includes a first device die, and a first encapsulating material encapsulating the first device die therein. A bottom surface of the first device die... |
| 2017/0133350 |
SYSTEMS AND METHODS FOR PACKAGE ON PACKAGE THROUGH MOLD INTERCONNECTS Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first... |
| 2017/0133349 |
METHOD OF PACKAGING INTEGRATED CIRCUIT DIE AND DEVICE A package substrate having an opening and through-substrate interconnect structures is attached to a temporary carrier such as an adhesive film. The active... |
| 2017/0133348 |
LIGHT EMITTING DEVICE The present disclosure relates to a light emitting device using an organic EL. The light emitting device includes an organic EL panel where a plurality of... |
| 2017/0133347 |
METHOD FOR MANUFACTURING SUBSTRATES A manufacturing method including supplying a first substrate including a first face designated front face, the front face being made of a III-V type... |
| 2017/0133346 |
Bump Structure for Yield Improvement A bump structure for electrically coupling semiconductor components is provided. The bump structure includes a first bump on a first semiconductor component... |
| 2017/0133345 |
BONDING SUBSTRATES USING SOLDER SURFACE TENSION DURING SOLDER REFLOW FOR
THREE DIMENSIONAL SELF-ALIGNMENT OF... Methods are provided for bonding substrates together using alignment structures and solder reflow techniques which achieve self-alignment in three dimensions,... |
| 2017/0133344 |
SEMICONDUCTOR DEVICE WITH A RESIN LAYER AND METHOD OF MANUFACTURING THE
SAME A semiconductor device includes a substrate, a semiconductor chip having a first surface bonded to the substrate and a second surface that is opposite to the... |
| 2017/0133343 |
INTEGRATED CIRCUIT DEVICE An integrated circuit device including a semiconductor substrate, a first bonding pad structure, a second bonding pad structure, a third bonding pad structure,... |
| 2017/0133342 |
Bond Wire Connection An integrated circuit package is provided. The integrated circuit package comprises: a die; a lead; and a bond wire comprising a first end coupled to the die... |
| 2017/0133341 |
SEMICONDUCTOR PACKAGES WITH AN INTERMETALLIC LAYER A method of forming a semiconductor package. Implementations include forming on a die backside an intermediate metal layer having multiple sublayers, each... |
| 2017/0133340 |
METHOD FOR PRODUCING A CHIP MODULE The invention concerns a method for producing a chip module having a carrier substrate and at least one chip arranged on the carrier substrate, as well as a... |
| 2017/0133339 |
SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME A semiconductor device with an under-bump metallurgy (UBM) over a dielectric is provided. The UBM has a trench configured to be offset from a central point of... |
| 2017/0133338 |
MULTILAYER PILLAR FOR REDUCED STRESS INTERCONNECT AND METHOD OF MAKING
SAME A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar... |
| 2017/0133337 |
FABRICATION METHOD OF PACKAGING SUBSTRATE A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and... |
| 2017/0133336 |
INTERCONNECT STRUCTURES AND METHODS FOR FABRICATING INTERCONNECT
STRUCTURES A method of fabricating an interconnect structure includes providing a semiconductor structure and performing a first spin resist and bake cycle. The first... |
| 2017/0133335 |
SEMICONDUCTOR DEVICE AND METHOD OF MAKING A SEMICONDUCTOR DEVICE A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, one or more contacts located on... |
| 2017/0133334 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF A semiconductor device and a manufacturing method thereof, which can reduce a number of manufacturing processes and/or can reduce a thickness of the... |
| 2017/0133333 |
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME Provided are a semiconductor device and a semiconductor package including the same. The semiconductor device comprises a semiconductor chip body including a... |
| 2017/0133332 |
POWER INTEGRATED MODULE A power integrated module, including at least one first bridge formed in a chip, wherein the first bridge includes: a first upper bridge switch, formed by a... |
| 2017/0133331 |
SEMICONDUCTOR DEVICE A semiconductor device includes a first circuit 1 and a second circuit 2 that are connected in series, a first terminal T1 that applies a first potential to a... |
| 2017/0133330 |
Semiconductor Device and Method of Controlling Warpage in Reconstituted
Wafer A semiconductor device has a substrate with a stiffening layer disposed over the substrate. The substrate has a circular shape or rectangular shape. A... |
| 2017/0133329 |
2.5D ELECTRONIC PACKAGE A 2.5D electronic package is provided in which at least one integrated circuit is mounted on an interposer that is mounted on a package substrate. To reduce... |
| 2017/0133328 |
BOTTOM PROCESSING Embodiments disclosed herein generally relate to methods and apparatus for processing of the bottom surface of a substrate to counteract thermal stresses... |
| 2017/0133327 |
ELECTRIC MODULE COMPRISING A TENSIONING DEVICE An electrical module includes at least one electrical component and at least one hollow body which is filled or can be filled with a medium, particularly a... |
| 2017/0133326 |
WAFER LEVEL FAN-OUT WITH ELECTROMAGNETIC SHIELDING The present disclosure relates to an integrated circuit module with electromagnetic shielding. The integrated circuit module includes a die with an... |
| 2017/0133325 |
METHODS OF SELF-FORMING BARRIER FORMATION IN METAL INTERCONNECTION
APPLICATIONS A method of forming a self-forming barrier includes selectively removing a portion of a semiconductor dielectric layer to form a three-dimensional pattern... |
| 2017/0133324 |
CHEMICAL DIRECT PATTERN PLATING METHOD A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an... |
| 2017/0133323 |
Semiconductor Device and Method of Forming Inverted Pyramid Cavity
Semiconductor Package A semiconductor device has a first substrate. A conductive layer is formed over the first substrate. A first cavity is formed through the first substrate and... |
| 2017/0133322 |
Pad Structure Design in Fan-Out Package A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of non-solder electrical connectors... |
| 2017/0133321 |
APPARATUS AND METHOD FOR MITIGATING DYNAMIC IR VOLTAGE DROP AND
ELECTROMIGRATION AFFECTS An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically... |
| 2017/0133320 |
INTERCONNECT STRUCTURE WITH MISALIGNED METAL LINES COUPLED USING DIFFERENT
INTERCONNECT LAYER In some embodiments, an interconnect structure includes first and second metal lines, and an end-to-end portion. The first metal line is formed in a first... |
| 2017/0133319 |
METHOD, APPARATUS, AND SYSTEM FOR E-FUSE IN ADVANCED CMOS TECHNOLOGIES Methods, apparatus, and systems for fabricating and using a semiconductor device comprising a first conductive element; a second conductive element; and an... |
| 2017/0133318 |
Conductive Structure and Method of Forming the Same Conductive structures and method of manufacture thereof are disclosed. A barrier layer can line the first recess of a substrate. A first seed layer can be... |
| 2017/0133317 |
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes an interlayer insulating film, a first trench... |
| 2017/0133316 |
SEMICONDUCTOR DEVICE WITH STACKED TERMINALS A semiconductor device includes: a housing; a substrate inside the housing; first and second semiconductor circuits on the substrate; and first and second... |
| 2017/0133315 |
ELECTRONIC COMPONENT HOUSING PACKAGE, AND ELECTRONIC DEVICE COMPRISING
SAME An electronic component housing package includes an insulating base including an upper surface, the insulating base including a first cut-out portion and a... |
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