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Patent # Description
2017/0149462 Systems and Methods For Cancellation of Cross-Coupled Noise
Systems and methods for canceling cross-coupled satellite signals in a LNB IC include receiving a first satellite signal at a first input of the LNB IC and...
2017/0149461 METHOD AND APPARATUS FOR DISCRIMINATING BETWEEN VOICE SIGNALS
A method and apparatus for distinguishing voice signals that are played together over the same speaker employs spectral reshaping of one or more of the audio...
2017/0149460 RADIO FREQUENCY POWER AMPLIFICATION SYSTEM, RADIO FREQUENCY POWER AMPLIFICATION METHOD, TRANSMITTER, AND BASE...
A apparatus for radio frequency power amplification, a radio frequency power amplification method, a transmitter, and a base station that can reduce nonlinear...
2017/0149459 DISTORTION COMPENSATION DEVICE AND DISTORTION COMPENSATION METHOD
A distortion compensation device coupled to an amplifier configured to amplify power of a transmission signal, the distortion compensation device including a...
2017/0149458 DISTORTION COMPENSATION DEVICE AND DISTORTION COMPENSATION METHOD
A distortion compensation device includes an address generating unit, an LUT, and a multiplier. The address generating unit calculates the magnitude of a first...
2017/0149457 APPARATUS AND METHODS FOR TRANSCEIVER CALIBRATION
Apparatus and methods for transceiver calibration are provided. In certain configurations, a transceiver includes a transmit channel and an observation...
2017/0149456 ERROR CORRECTION ENCODER, ERROR CORRECTION DECODER, AND OPTICAL COMMUNICATION DEVICE INCLUDING THE SAME
Provided is an error correction encoder. The error correction encoder includes input nodes for receiving input words, first encoders for generating first...
2017/0149455 BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 4/15 AND...
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first...
2017/0149454 BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND...
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first...
2017/0149453 BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND...
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first...
2017/0149452 Flexible Polynomial-Based Interleaver
Techniques are disclosed relating to circuitry configured to interleave data, e.g., for use to process error correcting codes for wireless data transmission....
2017/0149451 METHOD OF SIMILARITY TESTING BY SYNDROMES AND APPARATUS THEREFORE
A method, executed by a processor, for determining similarity between messages includes calculating a syndrome of each of first and second messages with...
2017/0149450 TRANSMITTING APPARATUS AND INTERLEAVING METHOD THEREOF
A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a Low Density Parity Check (LDPC) codeword by LDPC...
2017/0149449 BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 16200 AND CODE RATE OF 3/15 AND...
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first...
2017/0149448 BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 4/15 AND...
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first...
2017/0149447 LOW DENSITY PARITY CHECK ENCODER HAVING LENGTH OF 16200 AND CODE RATE OF 4/15, AND LOW DENSITY PARITY CHECK...
A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory,...
2017/0149446 LDPC POST-PROCESSOR ARCHITECTURE AND METHOD FOR LOW ERROR FLOOR CONDITIONS
Post-processing circuitry for LDPC decoding includes check node processor for processing shifted LLR values, a hard decision decoder circuitry for receiving...
2017/0149445 Irregular Low Density Parity Check Processing System With Non-Uniform Scaling
An apparatus for decoding data includes a data decoding circuit configured to decode data encoded with an irregular low density parity check code based on a...
2017/0149444 ERROR CORRECTION USING CYCLIC CODE-BASED LDPC CODES
Techniques are described for joint encoding and decoding of information symbols. In one embodiment, a method for joint encoding includes, in part, obtaining a...
2017/0149443 APPARATUS AND METHOD FOR COMPRESSING CONTINUOUS DATA
Disclosed are an apparatus and method for compressing continuous data. The apparatus for compressing continuous data may include a data generator configured to...
2017/0149442 PAD ENCODING AND DECODING
A system, method and computer program product for encoding an input string of binary characters representing alphanumeric characters. A system includes: a...
2017/0149441 SPLIT GAIN SHAPE VECTOR CODING
The invention relates to an encoder and a decoder and methods therein for supporting split gain shape vector encoding and decoding. The method performed by an...
2017/0149440 METHOD FOR ADAPTIVELY REGULATING CODING MODE AND DIGITAL CORRECTION CIRCUIT THEREOF
A method for adaptively regulating a coding mode and a digital correction circuit thereof are provided. The method is for a successive-approximation-register...
2017/0149439 MULTI-ZONE DATA CONVERTERS
Aspects of a method and system for data converters having a transfer function with multiple operating zones. In some embodiments, an operating zone of the...
2017/0149438 FACILITATION OF INCREASED LOCKING RANGE TRANSISTORS
Transistors can be used for a variety of electronic-based applications. Therefore, transistor efficiency and performance is of importance. An apparatus is...
2017/0149437 Replica Cascode Bias Voltage-Controlled Oscillators
Embodiments relate to a voltage oscillator (VCO) that uses a replica bias circuit to generate a cascode bias voltage. The VCO generate an output periodic...
2017/0149436 SEMICONDUCTOR DEVICE HAVING IMPEDANCE CALIBRATION FUNCTION TO DATA OUTPUT BUFFER AND SEMICONDUCTOR MODULE...
Disclosed herein is a semiconductor device that includes a first transistor unit coupled to the data terminal, and a plurality of second transistor units...
2017/0149435 LEVEL SHIFTER AND PARALLEL-TO-SERIAL CONVERTER INCLUDING THE SAME
A level shifter circuit includes a level shifting unit configured to receive signals that may vary in a first range via a positive input terminal and a...
2017/0149434 LEVEL SHIFTER CIRCUIT, CORRESPONDING APPARATUS AND METHOD
A level shifter circuit includes: an input stage for receiving an input signal switchable between a first and a second input level and an output stage to...
2017/0149433 METHODS AND APPARATUS FOR CAPACITIVELY DETECTING KEY MOTION AND FINGER PRESENCE ON KEYBOARD KEYS
A keyboard including a plurality of key assemblies configured to be pressed by an input object. A subset of the plurality of key assemblies each includes a key...
2017/0149432 Integrated Interconnection Module Allowing Dielectric Shift Sensing Activation of a Variety of Occupancy Monitors
Disclosed is an integrated interconnect cable component for allowing the operation of dielectric shift sensor elements with a variety of control monitors...
2017/0149431 INSULATED GATE BIPOLAR TRANSISTOR DRIVING CIRCUIT
The present disclosure provides an IGBT driving circuit, including an optocoupler chip and a power amplification circuit. The optocoupler chip includes an...
2017/0149430 PACKAGED UNIDIRECTIONAL POWER TRANSISTOR AND CONTROL CIRCUIT THEREFORE
A packaged unidirectional power transistor comprises a package with a number of pins which provide a voltage and/or current connection between the outside and...
2017/0149429 RF Switch with Bypass Topology
An RF signal switch circuit that allows connection of any of N radio frequency (RF) input terminals to a switch output port, either in an in-circuit mode or in...
2017/0149428 CIRCUIT ARRANGEMENT FOR CONTROLLING POWER TRANSISTORS OF A POWER CONVERTER
A circuit arrangement for controlling power transistors of a power converter includes a logic circuit configured to generate a pulse-width modulation (PWM)...
2017/0149427 APPARATUS AND METHOD FOR REDUCING di/dt DURING POWER WAKE-UP
Described is an apparatus which comprises: a power gate transistor coupled to an ungated power supply node and a gated power supply node, the power gate...
2017/0149426 SWITCHING CIRCUIT
A switching circuit switches a first IGBT and a second IGBT. A control circuit is equipped with a first switching element that is configured to be able to...
2017/0149425 Switching Circuit
A switching circuit includes a wiring into which a parallel circuit of a first IGBT and a second IGBT is inserted, and a gate control circuit. The gate control...
2017/0149424 Ultra Low Power Reduced Coupling Clocked Comparator
A comparator circuit comprising a first node operable to receive a voltage during a precharge phase and a second node operable to receive the voltage during...
2017/0149423 APPARATUS FOR DETECTING VARIATION IN TRANSISTOR THRESHOLD VOLTAGE
A ring oscillator includes a plurality of inverters. A closed loop structure is formed by cascading the inverters. The inverter includes at least one sensitive...
2017/0149422 APPARATUSES AND METHODS FOR PROVIDING A SIGNAL WITH A DIFFERENTIAL PHASE MIXER
According to one embodiment, an apparatus is described. The apparatus comprises a first phase mixer circuit configured to receive a first signal and a second...
2017/0149421 AMPLIFIER
An amplifier includes a first voltage generating circuit that generates a first clamp voltage based on a reference voltage and a first voltage, a second...
2017/0149420 FREQUENCY MULTIPLIER
A frequency includes an input terminal, an output terminal, a transistor having a gate terminal which receives input of a signal including a first frequency...
2017/0149419 MULTI-BIT FLIP-FLOP WITH SOFT ERROR SUPPRESSION
A multi-bit flip-flop includes at least two storage stages. Each of the storage stages includes redundant latches to suppress state corruptions resulting from...
2017/0149418 High Resolution Capture
A high resolution capture circuit and integrated circuit chip are disclosed and include first and second capture delay lines and an oscillator delay line. The...
2017/0149417 PULSE WIDTH MODULATOR AND NON-TRANSITORY COMPUTER READABLE MEDIUM FOR STORING PROGRAM FOR PULSE WIDTH MODULATOR
The pulse width modulator includes a subtraction unit configured to perform subtraction between an m value digital signal and a pulse width modulation signal;...
2017/0149416 IMPROVED DESIGN METHOD OF TWO-STAGE FRM FILTER
An improved design method of a two-stage FRM filter includes the following steps: constructing an improved two-stage FRM filter; calculating passband and...
2017/0149415 FLOATING IMMITTANCE EMULATOR
The floating immittance emulator is presented in four embodiments in which four new topologies for emulating floating immittance functions are detailed. Each...
2017/0149414 FLOATING IMMITTANCE EMULATOR
The floating immittance emulator is presented in four embodiments in which four new topologies for emulating floating immittance functions are detailed. Each...
2017/0149413 FLOATING IMMITTANCE EMULATOR
The floating immittance emulator is presented in four embodiments in which four new topologies for emulating floating immittance functions are detailed. Each...
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