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Patent # Description
2017/0148803 METHOD FOR FORMING FLASH MEMORY STRUCTURE
Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a word line cell over a...
2017/0148802 Integrated Assemblies and Methods of Forming Integrated Assemblies
Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces...
2017/0148801 ANTIFUSE-TYPE ONE TIME PROGRAMMING MEMORY CELL AND ARRAY STRUCTURE WITH SAME
An antifuse-type one time programming memory cell, comprising: a first select transistor, wherein a first drain/source terminal of the first select transistor...
2017/0148800 THREE DIMENSIONAL NAND DEVICE CONTAINING DIELECTRIC PILLARS FOR A BURIED SOURCE LINE AND METHOD OF MAKING THEREOF
A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of...
2017/0148799 HYBRID LOGIC AND SRAM CONTACTS
The method includes forming a first opening in a dielectric layer exposing a source drain region of an SRAM device and forming a second opening in the...
2017/0148798 SELECTIVE EPITAXY GROWTH FOR SEMICONDUCTOR DEVICES WITH FIN FIELDEFFECT TRANSISTORS (FINFET)
A method for forming a semiconductor device includes depositing spacer material on a first sidewall and a second sidewall of a fin formed on a substrate. An...
2017/0148797 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
A semiconductor device may include a first active fin, a plurality of second active fins, a first source/drain layer structure, and a second source/drain layer...
2017/0148796 SELECTIVE EPITAXY GROWTH FOR SEMICONDUCTOR DEVICES WITH FIN FIELD-EFFECT TRANSISTORS (FINFET)
A method for forming a semiconductor device includes depositing spacer material on a first sidewall and a second sidewall of a fin formed on a substrate. The...
2017/0148795 Two-Transistor SRAM Semiconductor Structure and Methods of Fabrication
A two-transistor memory cell based upon a thyristor for an SRAM integrated circuit is described together with a process for fabricating it. The memory cell can...
2017/0148794 P-CHANNEL MULTI-TIME PROGRAMMABLE (MTP) MEMORY CELLS
Multi-time programmable (MTP) memory cells, integrated circuits including MTP memory cells, and methods for fabricating MTP memory cells are provided. In an...
2017/0148793 DUAL CHANNEL MATERIAL FOR finFET FOR HIGH PERFORMANCE CMOS
Silicon fins are formed in a bulk silicon substrate and thereafter trench isolation regions are formed between each silicon fin. The silicon fins in nFET and...
2017/0148792 Semiconductor Devices Including Gate Structures With Oxygen Capturing Films
A semiconductor device includes: a semiconductor substrate including an active region and a gate structure on the active region. The gate structure includes a...
2017/0148791 MACRO-TRANSISTOR DEVICES
Macro-transistor structures are disclosed. In some cases, the macro-transistor structures have the same number of terminals and properties similar to...
2017/0148790 Stop Layer Through Ion Implantation For Etch Stop
A process for etching a bulk integrated circuit substrate to form features on the substrate, such as fins, having substantially vertical walls comprises...
2017/0148789 EFFECTIVE DEVICE FORMATION FOR ADVANCED TECHNOLOGY NODES WITH AGGRESSIVE FIN-PITCH SCALING
After forming a gate stack straddling a portion of each semiconductor fin of a plurality of semiconductor fins located over a substrate, a gate liner is formed...
2017/0148788 FIN PITCH SCALING FOR HIGH VOLTAGE DEVICES AND LOW VOLTAGE DEVICES ON THE SAME WAFER
A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second...
2017/0148787 MULTI-VT GATE STACK FOR III-V NANOSHEET DEVICES WITH REDUCED PARASITIC CAPACITANCE
A nanosheet field effect transistor design in which the threshold voltage is adjustable by adjusting the composition of the gate. The channel of the nanosheet...
2017/0148786 SEMICONDUCTOR DEVICE
A semiconductor device comprising: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type...
2017/0148785 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate including, on a first surface, first trenches and a second trench linked to each of the first...
2017/0148784 INTEGRATION OF ACTIVE POWER DEVICE WITH PASSIVE COMPONENTS
A method of integrating at least one passive component and at least one active power device on a same substrate includes: forming a substrate having a first...
2017/0148783 FIELD EFFECT TRANSISTOR (FET) STRUCTURE WITH INTEGRATED GATE CONNECTED DIODES
A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect...
2017/0148781 DRIVER CIRCUIT, METHOD OF MANUFACTURING THE DRIVER CIRCUIT, AND DISPLAY DEVICE INCLUDING THE DRIVER CIRCUIT
Provided are a driver circuit which suppresses damage of a semiconductor element due to ESD in a manufacturing process, a method of manufacturing the driver...
2017/0148780 ELECTRONIC DEVICE, IN PARTICULAR FOR PROTECTION AGAINST OVERVOLTAGES
An electronic device is formed by a sequence of at least two thyristors coupled in series in a same conduction direction. Each thyristor has a gate of a first...
2017/0148779 Cell Circuit and Layout with Linear Finfet Structures
A cell circuit and corresponding layout is disclosed to include linear-shaped diffusion fins defined to extend over a substrate in a first direction so as to...
2017/0148778 Package Structures and Methods of Forming the Same
Packages structure and methods of forming them are discussed. A structure includes a first die, a first encapsulant at least laterally encapsulating the first...
2017/0148777 OPTOELECTRONIC DEVICE WITH LIGHT-EMITTING DIODES COMPRISING AT LEAST ONE ZENER DIODE
The invention relates to an optoelectronic device (1) comprising light-emitting diodes produced in a material mostly comprising a same semiconductor compound...
2017/0148776 LED LIGHTING APPARATUS
An LED lighting apparatus includes an LED substrate, a LED chip, a sealing resin member, and a reflecting face. The LED substrate has a main surface. The LED...
2017/0148775 LED LIGHT EMITTING DEVICE MANUFACTURING METHOD AND LED LIGHT EMITTING DEVICE
Disclosed are an LED light emitting device and its manufacturing method. A blue LED chip specification is selected, a green phosphor and the blue LED chip are...
2017/0148774 PACKAGE-ON-PACKAGE MODULES, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS INCLUDING THE SAME
Package-on-package (PoP) modules are provided. The PoP module includes a lower package and an upper package disposed over the lower package. The lower package...
2017/0148773 LIGHT EMITTING DEVICE REFLECTIVE BANK STRUCTURE
Reflective bank structures for light emitting devices are described. The reflective bank structure may include a substrate, an insulating layer on the...
2017/0148772 LIGHT EMITTING APPARATUS
A light emitting apparatus is disclosed. The light emitting apparatus includes a light-transmissive substrate having a top surface and a bottom surface, at...
2017/0148771 LIGHT SOURCE MODULE, DISPLAY PANEL, AND DISPLAY APPARATUS INCLUDING THE SAME
A light source module includes a circuit board having a plurality of chip mounting regions, the plurality of chip mounting regions respectively having at least...
2017/0148770 SEMICONDUCTOR MODULE
A semiconductor module includes upper arms and lower arms for three phases, heat sinks, a main circuit side bus bar, an output terminal side bus bar, a control...
2017/0148769 INTERCONNECT STRUCTURES WITH INTERMETALLIC PALLADIUM JOINTS AND ASSOCIATED SYSTEMS AND METHODS
Interconnect structures with intermetallic palladium joints are disclosed herein. In one embodiment, a method of forming an interconnect structure includes...
2017/0148768 INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING SAME
Packages and methods of manufacture thereof are described. A package may include a first package and a die structure disposed over the first package. The first...
2017/0148767 3DIC Packages with Heat Dissipation Structures
A package includes a first die and a second die underlying the first die and in a same first die stack as the first die. The second die includes a first...
2017/0148766 SEMICONDUCTOR PACKAGE
A stacked semiconductor package in an embodiment includes a first semiconductor package including a first circuit board and a first semiconductor element...
2017/0148765 Singulation and Bonding Methods and Structures Formed Thereby
Methods of singulation and bonding, as well as structures formed thereby, are disclosed. A method includes singulating a first chip and after the singulating...
2017/0148764 MULTI-CHIP MICROELECTRONIC ASSEMBLY WITH BUILT-UP FINE-PATTERNED CIRCUIT STRUCTURE
A microelectronic assembly includes a dielectric element having bumps projecting from a first surface thereof, the bumps having end surfaces flush with a...
2017/0148763 HYBRID 3D/2.5D INTERPOSER
Representative implementations of devices and techniques provide a hybrid interposer for 3D or 2.5D package arrangements. A quantity of pockets is formed on a...
2017/0148762 METHOD AND STRUCTURE FOR SEMICONDUCTOR DIE REMOVAL REWORK
Disclosed are processes and apparatuses for semiconductor die removal and rework, including thin dies. In one aspect the process involves the use of a...
2017/0148761 METHOD OF FABRICATING SEMICONDUCTOR PACKAGE
The present invention provides a semiconductor package and a method of fabricating the same, including: placing in a groove of a carrier a semiconductor...
2017/0148760 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor chip includes a chip body and a plurality of solder-including electrodes provided on an element-formation surface of the chip body. A packaging...
2017/0148759 BONDING APPARATUS AND BONDING METHOD
A bonding apparatus 10 includes: a bonding head 18 configured to move a top camera 24 facing toward a bonding surface and a collet 22 disposed with an offset...
2017/0148758 Circuit Card Attachment for Enhanced Robustness of Thermal Performance
Exemplary embodiments of the invention include a method and apparatus for assembling a semiconductor device. The method may include heating the semiconductor...
2017/0148757 SEMICONDUCTOR DEVICE AND METHOD FOR MAKING SEMICONDUCTOR DEVICE
A semiconductor device includes: a substrate including a base member having a main surface and a back surface facing opposite in a thickness direction; a...
2017/0148756 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A semiconductor structure and a method for forming the same are provided. The method includes: providing a first semiconductor workpiece; depositing a first...
2017/0148755 FULLY MOLDED PERIPHERAL PACKAGE ON PACKAGE DEVICE
A method of making a semiconductor device can comprise providing a temporary carrier comprising a semiconductor die mounting site, and forming an insulating...
2017/0148754 EXTRUSION-RESISTANT SOLDER INTERCONNECT STRUCTURES AND METHODS OF FORMING
Various embodiments include methods of forming interconnect structures, and the structures formed by such methods. In one embodiment, an interconnect structure...
2017/0148753 SEMICONDUCTOR DEVICES AND METHODS OF FORMING THE SAME
According to aspects provided herein, a semiconductor device may include a bump providing improved reliability and reduced size. In some aspects, a conductive...
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