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Patent # Description
2017/0148752 CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
A chip package includes a substrate, an isolation layer, a redistribution layer, a passivation layer, a first conductive layer, a second conductive layer, and...
2017/0148751 SEMICONDUCTOR DEVICE
A semiconductor device includes a first semiconductor chip including a first plurality of wiring layers, and a first coil, a first bonding pad, and first dummy...
2017/0148750 ON-DIE INDUCTOR WITH IMPROVED Q-FACTOR
Described is an apparatus which comprises: a substrate; a plurality of holes formed as vias (e.g., through-silicon-vias (TSVs)) in the substrate; and a metal...
2017/0148749 REDUCED-WARPAGE LAMINATE STRUCTURE
A laminate structure includes a conductive layer and a dielectric layer in contact with the conductive layer, the dielectric layer comprises a selectively...
2017/0148748 THREE-DIMENSIONAL SEMICONDUCTOR DEVICES WITH SCRIBE LINE REGION STRUCTURES
Three-dimensional (3D) semiconductor devices may be provided. A 3D semiconductor device may include a substrate including a chip region and a scribe line...
2017/0148747 STRESS RELIEF IN SEMICONDUCTOR WAFERS
Methods for compensating for warpage in a semiconductor structure comprising an epitaxial layer grown on a semiconductor substrate. The methods include forming...
2017/0148746 SEMICONDUCTOR DEVICE PACKAGE
A semiconductor device package includes a conductive base, and a cavity defined from a first surface of the conductive base, the cavity having a bottom surface...
2017/0148745 ELECTRICAL PACKAGE INCLUDING BIMETAL LID
Electrical package including bimetal lid. The electrical package includes: an organic substrate; a semiconductor chip electrically connected to electrical pads...
2017/0148744 SUBSTRATE-LESS INTEGRATED COMPONENTS
Packages including substrate-less integrated components and methods of fabrication are described are described. In an embodiment, a packaging method includes...
2017/0148743 Semiconductor chip package comprising side wall marking
The semiconductor chip package comprises a semiconductor chip, and an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body...
2017/0148742 SEMICONDUCTOR CHIP, METHOD OF MANUFACTURING THE SEMICONDUCTOR CHIP, AND SEMICONDUCTOR PACKAGE AND DISPLAY...
A semiconductor chip having an improved structure without an investment in photolithography equipment, a method of manufacturing the semiconductor chip, and a...
2017/0148741 ADVANCED METALLIZATION FOR DAMAGE REPAIR
An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the...
2017/0148740 ADVANCED METALLIZATION FOR DAMAGE REPAIR
An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the...
2017/0148739 SELECTIVE DIFFUSION BARRIER BETWEEN METALS OF AN INTEGRATED CIRCUIT DEVICE
Embodiments of the present disclosure describe a selective diffusion barrier between metals of an integrated circuit (IC) device and associated techniques and...
2017/0148738 ADVANCED COPPER INTERCONNECTS WITH HYBRID MICROSTRUCTURE
A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the...
2017/0148737 METHOD AND STRUCTURE FOR ESTABLISHING INTERCONNECTS IN PACKAGES USING THIN INTERPOSERS
An interposer structure and a method of interconnecting first and second semiconductor dies are provided. A splice interposer is attached to a top surface of a...
2017/0148736 STRUCTURE AND PROCESS FOR W CONTACTS
Structures and processes include a single metallization step for forming a metal nitride liner layer suitable for contact formation. The structure and...
2017/0148735 Interconnect Structure for Semiconductor Devices
An interconnect and a method of forming an interconnect for a semiconductor device is provided. Conductive lines having different widths are formed. Wider...
2017/0148734 METHOD OF FABRICATING ANTI-FUSE FOR SILICON ON INSULATOR DEVICES
A method includes depositing a first hard mask layer on a first substrate; lithographically patterning and etching the first substrate to form a semiconductor...
2017/0148733 METHOD OF FABRICATING ANTI-FUSE FOR SILICON ON INSULATOR DEVICES
A method includes depositing a first hard mask layer on a first substrate; lithographically patterning and etching the first substrate to form a semiconductor...
2017/0148732 SEMICONDUCTOR DEVICE
An improvement is achieved in the performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a wiring structure formed...
2017/0148731 Methods Of Forming A Semiconductor Device Comprising First And Second Nitride Layers
A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well...
2017/0148730 CRITICAL DIMENSION SHRINK THROUGH SELECTIVE METAL GROWTH ON METAL HARDMASK SIDEWALLS
A method for fabricating a self-aligned via structure includes forming a tri-layer mask on an ILD layer over a lower metal wiring layer, the tri-layer mask...
2017/0148729 ADVANCED METALLIZATION FOR DAMAGE REPAIR
An electrical contact structure for an integrated circuit device is described. A first patterned dielectric layer comprising at least one contact hole, the...
2017/0148728 DECOUPLING CAPACITORS AND ARRANGEMENTS
Various embodiments of transistor assemblies, integrated circuit devices, and related methods are disclosed herein. In some embodiments, a transistor assembly...
2017/0148727 SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME
A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion...
2017/0148726 SEMICONDUCTOR PROCESSING METHOD AND SEMICONDUCTOR DEVICE
A semiconductor processing method and semiconductor device are described. The processing method includes forming a p-doped germanium structure on a substrate,...
2017/0148725 PACKAGE OF A CONTROLLER AND SCREEN CONTROL MODULE WITH THE SAME
A screen control module of a mobile electronic device has at least one controller formed on a circuit board. The circuit board has multiple solder pads formed...
2017/0148724 Package Substrate
This disclosure provides a package substrate which includes a rigid dielectric material layer, a first wiring layer having at least one first metal wire formed...
2017/0148723 MATERIALS, STRUCTURES AND METHODS FOR MICROELECTRONIC PACKAGING
Highly reliable interconnections for microelectronic packaging. In one embodiment, dielectric layers in a build-up interconnect have a gradation in glass...
2017/0148722 SEMICONDUCTOR PACKAGES AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES
A device is disclosed. The device includes a carrier substrate having first and second major surfaces. The first surface includes a die region and contact pads...
2017/0148721 Semiconductor Device and Method of Forming Openings Through Insulating Layer Over Encapsulant for Enhanced...
A semiconductor device has a semiconductor die mounted to a carrier. An encapsulant is deposited over the semiconductor die and carrier. The carrier is...
2017/0148720 CIRCUIT SUBSTRATE AND SEMICONDUCTOR PACKAGE STRUCTURE
A circuit substrate for a chip bonding thereon includes a core substrate having a chip-side surface and a bump-side surface opposite to the chip-side surface,...
2017/0148719 THROUGH-ELECTRODE SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND SEMICONDUCTOR DEVICE IN WHICH THROUGH-ELECTRODE...
A through-electrode substrate includes a base including a first surface and a second surface mutually opposing each other, and a through-electrode arranged in...
2017/0148718 WIRING BOARD, ELECTRONIC DEVICE, AND ELECTRONIC MODULE
A wiring board according to the present invention includes: an insulating base including a main face, a side face, and a notch portion opened in the main face...
2017/0148717 METHOD OF MANUFACTURING WIRING SUBSTRATE AND WIRING SUBSTRATE
To provide a technique capable of easily forming a resin opening of a desired shape. As a solution, a base is prepared which has a first surface region and a...
2017/0148716 ELECTRONIC PACKAGE AND METHOD OF FABRICATING THE SAME
A met of fabricating an electronic package is provided, g: providing a carrier body haying a first surface formed with a plurality of recessed portions, and a...
2017/0148715 PACKAGE SYSTEM FOR INTEGRATED CIRCUITS
A package system comprising a first interconnect structure arranged over a first surface of a first substrate; a plurality of first through silicon via (TSV)...
2017/0148714 GROUND VIA CLUSTERING FOR CROSSTALK MITIGATION
Embodiments of the present disclosure are directed towards techniques and configurations for ground via clustering for crosstalk mitigation in integrated...
2017/0148713 CONNECTION MEMBER, SEMICONDUCTOR DEVICE, AND STACKED STRUCTURE
A connection member according to an embodiment includes a dielectric material, a penetrating via penetrating through the dielectric material, a first metal...
2017/0148712 METHOD AND SYSTEM FOR IMPROVED MATCHING FOR ON-CHIP CAPACITORS
Methods and systems for improved matching of on-chip capacitors may comprise a semiconductor die with an on-chip capacitor comprising one or more metal layers....
2017/0148711 SEMICONDUCTOR PACKAGE
Provided is a semiconductor package. The semiconductor package includes: a first die that is a monolithic type die, a driver circuit and a low-side output...
2017/0148710 Power electronic switching device comprising a plurality of potential surfaces
A power electronic switching device having plurality of potential surfaces. At least two different potentials are respectively assigned to at least one of the...
2017/0148709 LEAD FRAME AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A first lead terminal, a second lead terminal provided parallel to the first lead terminal, and a tie bar connecting the first lead terminal and the second...
2017/0148708 STRETCHABLE SEMICONDUCTOR PACKAGES AND SEMICONDUCTOR DEVICES INCLUDING THE SAME
A semiconductor package includes an extendible molding member, a chip embedded in the molding member to have a warped shape, and connectors disposed in the...
2017/0148707 SEMICONDUCTOR DEVICE
An ESD protection device including a Si substrate with an ESD protection circuit formed at the surface of the substrate; pads formed on the Si substrate; a...
2017/0148706 SILICONE-BASED THERMAL INTERFACE MATERIALS
In an example, a silicone-based thermal interface material includes a thermally conductive material and a silicone-based polymeric material having a solubility...
2017/0148705 SEMICONDUCTOR PACKAGE WITH INTEGRATED OUTPUT INDUCTOR ON A PRINTED CIRCUIT BOARD
A semiconductor package includes a semiconductor die comprising a control transistor and a sync transistor, an integrated output inductor comprising a winding...
2017/0148704 ELECTRICAL PACKAGE INCLUDING BIMETAL LID
Electrical package including bimetal lid. The electrical package includes: an organic substrate; a semiconductor chip electrically connected to electrical pads...
2017/0148703 SEMICONDUCTOR DEVICE
A semiconductor device includes: a processor having a heat sink mounted thereon; and an optical module having a heat transfer interposer, wherein the heat sink...
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