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Patent # Description
2017/0148702 DISPLAY DEVICE
According to one embodiment, a display device includes a first substrate including a display area containing a plurality of pixels and a non-display area, a...
2017/0148701 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate; a semiconductor layer; a first protective film; a first adhesive layer disposed on the first protective film; an...
2017/0148700 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF A SEMICONDUCTOR DEVICE
A manufacturing method of a semiconductor device includes: forming a mark on a surface of a semiconductor wafer, at least a part of the mark being disposed in...
2017/0148699 FAN-OUT SEMICONDUCTOR PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME
A fan-out semiconductor package and an electronic device including the same are provided. The fan-out semiconductor package includes a semiconductor chip; an...
2017/0148698 CONDUCTIVE PATHS THROUGH DIELECTRIC WITH A HIGH ASPECT RATIO FOR SEMICONDUCTOR DEVICES
Conductive paths through a dielectric are described that have a high aspect ratio for semiconductor devices. In one example, a semiconductor device package has...
2017/0148697 SEMICONDUCTOR DEVICE AND METHOD OF MAKING A SEMICONDUCTOR DEVICE
A semiconductor device and a method of making the same. The device includes a semiconductor substrate having a major surface, a backside and side surfaces...
2017/0148696 FINE PITCH BVA USING RECONSTITUTED WAFER WITH AREA ARRAY ACCESSIBLE FOR TESTING
A method for simultaneously making a plurality of microelectronic packages by forming an electrically conductive redistribution structure along with a...
2017/0148695 USE OF AN EXTERNAL GETTER TO REDUCE PACKAGE PRESSURE
A surface defined by a wafer level package (WLP) region and an external region, and A system and method for forming a wafer level package. In one example, a...
2017/0148694 CHIP PACKAGE AND MANUFACTURING METHOD THEREOF
A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second...
2017/0148693 CONTAINER FOR HOUSING ELECTRONIC COMPONENT AND ELECTRONIC DEVICE
A container for housing an electronic component includes: a container body including a bottom plate and a polygonal side wall surrounding a central region of...
2017/0148692 SEMICONDUCTOR PACKAGE INCLUDING A SEMICONDUCTOR DIE HAVING REDISTRIBUTED PADS
A semiconductor package that includes a semiconductor die, an insulation around the die, and a conforming conductive pad coupled to an electrode of the die.
2017/0148691 METHODS AND SYSTEMS FOR IMAGING AND CUTTING SEMICONDUCTOR WAFERS AND OTHER SEMICONDUCTOR WORKPIECES
Methods and systems for imaging and cutting semiconductor wafers and other microelectronic device substrates are disclosed herein. In one embodiment, a system...
2017/0148690 Thin-Film Fabrication System Employing Mechanical Stress Measurement
A system deposits a film on a substrate while determining mechanical stress experienced by the film. A substrate is provided in a deposition chamber. A support...
2017/0148689 METHOD OF FORMING PATTERN OF SEMICONDUCTOR DEVICE FROM WHICH VARIOUS TYPES OF PATTERN DEFECTS ARE REMOVED
The method includes classifying sample pattern data into a standard normal group and a standard weak group based on a first criterion. The method further...
2017/0148688 PREVENTING BURIED OXIDE GOUGING DURING PLANAR AND FINFET PROCESSING ON SOI
A method for preventing damage to the insulator layer of a semiconductor device during creation of fin field effect transistor (FinFET) includes obtaining a...
2017/0148687 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device may include forming first trenches that define active patterns extending in a first direction on a substrate,...
2017/0148686 FORMING A SEMICONDUCTOR STRUCTURE FOR REDUCED NEGATIVE BIAS TEMPERATURE INSTABILITY
An approach to forming a semiconductor structure with improved negative bias temperature instability includes diffusing fluorine atoms into a semiconductor...
2017/0148685 DUAL CHANNEL MATERIAL FOR finFET FOR HIGH PERFORMANCE CMOS
Silicon fins are formed in a bulk silicon substrate and thereafter trench isolation regions are formed between each silicon fin. The silicon fins in nFET and...
2017/0148684 FIELD EFFECT TRANSISTOR INCLUDING STRAINED GERMANIUM FINS
In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region...
2017/0148683 STACKED NANOWIRE SEMICONDUCTOR DEVICE
A semiconductor device a first epitaxially grown source/drain region comprising a first material arranged on a first fin, a second epitaxially grown...
2017/0148682 FINFET WITH POST-RMG GATE CUT
In a FinFET device, the gate cut is performed post-RMG. This allows PC-past-RX to be scaled to the thickness of the gate stack, thus reducing PC end parasitic...
2017/0148681 FIN PITCH SCALING FOR HIGH VOLTAGE DEVICES AND LOW VOLTAGE DEVICES ON THE SAME WAFER
A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second...
2017/0148680 FIELD EFFECT TRANSISTOR INCLUDING STRAINED GERMANIUM FINS
In one example, a device includes a p-type field effect transistor region and n-type field effect transistor region. The p-type field effect transistor region...
2017/0148679 SEMICONDUCTOR PACKAGE, SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A semiconductor package is disclosed, which includes: a packaging substrate; a semiconductor element disposed on the packaging substrate in a flip-chip manner;...
2017/0148678 APPARATUS AND METHODS FOR FILLING A WAFER VIA WITH SOLDER
A wafer via solder filling device includes a solder bath comprising an accommodation space for accommodating a molten solder, with an open top, and an air...
2017/0148677 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME
A semiconductor memory device is disclosed. The semiconductor memory device includes a substrate including cell and peripheral regions, a stack on the cell...
2017/0148676 Low-K Dielectric Layer and Porogen
A system and method for a low-k dielectric layer are provided. A preferred embodiment comprises forming a matrix and forming a porogen within the matrix. The...
2017/0148675 STRUCTURE AND PROCESS FOR W CONTACTS
Structures and processes include a single metallization step for forming a metal nitride liner layer suitable for contact formation. The structure and...
2017/0148674 THROUGH SUBSTRATE VIA LINER DENSIFICATION
Apparatuses and methods are disclosed herein for densification of through substrate insulating liners. An example method may include forming a through...
2017/0148673 SEMICONDUCTOR VIA STRUCTURE WITH LOWER ELECTRICAL RESISTANCE
A semiconductor device and method of making the same, wherein in accordance with an embodiment of the present invention, the device includes a first conductive...
2017/0148672 SEMICONDUCTOR STRUCTURES HAVING LOW RESISTANCE PATHS THROUGHOUT A WAFER
A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low...
2017/0148671 Semiconductor Device and Process
A metal first, via first process for forming interconnects within a metallization layer of a semiconductor device is provided. In an embodiment a conductive...
2017/0148670 METHODS FOR FORMING LOW-RESISTANCE CONTACTS THROUGH INTEGRATED PROCESS FLOW SYSTEMS
Methods for forming metal contacts having tungsten liner layers are provided herein. In some embodiments, a method of processing a substrate includes: exposing...
2017/0148669 METHOD, APPARATUS, AND SYSTEM FOR MOL INTERCONNECTS WITHOUT TITANIUM LINER
Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate;...
2017/0148668 HDP FILL WITH REDUCED VOID FORMATION AND SPACER DAMAGE
A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first...
2017/0148667 METHOD FOR FABRICATING SEMICONDUCTOR STRUCTURE WITH PASSIVATION SIDEWALL BLOCK
A semiconductor structure and a method for forming the semiconductor structure are provided. The method includes receiving a substrate with two sections of...
2017/0148666 DEVICE MANUFACTURE AND PACKAGING METHOD THEREOF
Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive...
2017/0148664 METHOD FOR THINNING SUBSTRATES
According to various embodiments, a method may include: providing a substrate having a first side and a second side opposite the first side; forming a buried...
2017/0148663 Method of Manufacturing a Semiconductor Device Having a Vertical Edge Termination Structure
A method of manufacturing a semiconductor device includes forming a frame trench extending from a first surface into a base substrate, forming, in the frame...
2017/0148662 SEMICONDUCTOR STRUCTURES INCLUDING MIDDLE-OF-LINE (MOL) CAPACITANCE REDUCTION FOR SELF-ALIGNED CONTACT IN GATE...
A semiconductor structure including one or more semiconductor devices on a wafer. The one or more devices having source/drain junctions. The semiconductor...
2017/0148661 ZIG-ZAG TRENCH STRUCTURE TO PREVENT ASPECT RATIO TRAPPING DEFECT ESCAPE
A method of fabricating a semiconductor device can include the following steps: (i) providing an initial sub-assembly including a trench-defining layer having...
2017/0148660 SUBSTRATE HOLDING APPARATUS
A substrate holding apparatus that can minimize a deflection amount of a substrate due to its own weight and can suppress vibration of the substrate at the...
2017/0148659 ADHESIVE COMPOSITION, LAMINATE, AND STRIPPING METHOD
An adhesive composition for temporarily attaching a substrate to a support plate which supports the substrate, including a thermoplastic resin and a release...
2017/0148658 THIN SUBSTRATE ELECTROSTATIC CHUCK SYSTEM AND METHOD
In various aspects of the disclosure, a semiconductor substrate processing system may include an electrostatic chuck for holding a semiconductor substrate...
2017/0148657 MATCHED TCR JOULE HEATER DESIGNS FOR ELECTROSTATIC CHUCKS
A substrate support for supporting a substrate in a substrate processing system includes a plurality of thermal elements. The thermal elements are arranged in...
2017/0148656 ALIGNMENT METHOD, PATTERN FORMATION SYSTEM, AND EXPOSURE DEVICE
According to one embodiment, an alignment method includes calculating a position gap of a predetermined point in a device area of a wafer based on a stress...
2017/0148655 POLISHING METHOD
A polishing method capable of obtaining a stable film thickness without being affected by a difference in measurement position is disclosed. The polishing...
2017/0148654 ON-BOARD METROLOGY (OBM) DESIGN AND IMPLICATION IN PROCESS TOOL
Implementations of the present disclosure generally relate to an improved factory interface that is coupled to an on-board metrology housing configured for...
2017/0148653 GAS TEMPERATURE MEASUREMENT METHOD AND GAS INTRODUCTION SYSTEM
There is provided a method of measuring a temperature of a gas in a line connected to a gas supply source and a decompressor, the line being divided by a...
2017/0148652 SPIN CHUCK WITH IN SITU TEMPERATURE MONITORING
A device for processing wafer-shaped articles comprises a rotary chuck mounted for rotation within a surrounding enclosure. The rotary chuck has mounted...
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