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Patent # Description
2017/0147539 GENERATION APPARATUS, PROGRAM, AND GENERATION METHOD
A generation apparatus that generates a mapping between individual properties included in an object in a program and individual elements of a structured...
2017/0147538 METHODS, DEVICES, AND COMPUTER-READABLE MEDIUM FOR INPUT PROCESSING
Methods, devices, and computer-readable storage medium are disclosed for inputting content coded in a sequence of key presses by a user of an application...
2017/0147537 Method, apparatus and system for reproducing a document defined in a page description language
A method of reproducing a document defined in a page description language (PDL) data structure. The PDL data structure defining content of the document...
2017/0147536 TEXT BROWSING, EDITING AND CORRECTION METHODS FOR AUTOMOTIVE APPLICATIONS
An automotive text display arrangement is described which includes a driver text display positioned directly in front of an automobile driver and displaying a...
2017/0147535 IDENTIFYING FONTS USING CUSTOM LIGATURES
A method for identifying a font displayed within an electronic document. In one embodiment, the method includes a computer processor identifying a string of...
2017/0147534 TRANSFORMATION OF THIRD-PARTY CONTENT FOR NATIVE INCLUSION IN A PAGE
Various technologies described herein pertain to creating transformed third-party content for inclusion in a page of a publisher for display on a client...
2017/0147533 Document Summary Feed Generation Method, Apparatus and System
Some embodiments of the invention provide a novel method for generating a page that contains summaries of a number of documents. In some embodiments, the page...
2017/0147532 Computer and Methods for Solving Math Functions
Computers and methods for performing mathematical functions are disclosed. An embodiment of a computer includes an operations level and a driver level. The...
2017/0147531 SPARSE MATRIX MULTIPLICATION USING A SINGLE FIELD PROGRAMMABLE GATE ARRAY MODULE
According to some embodiments, a computer-implemented method for performing sparse matrix dense matrix (SpMM) multiplication on a single field programmable...
2017/0147530 METHOD FOR PERFORMING SPARSE MATRIX-MATRIX MULTIPLICATION
Embodiments include performing sparse matrix-matrix multiplication. Aspects include receiving a first matrix and a second matrix, providing a pseudo-space for...
2017/0147529 MEMORY CONTROLLER AND SIMD PROCESSOR
Technology to suppress the drop in SIMD processor efficiency that occurs when exchanging two-dimensional data in a plurality of rectangular regions, between an...
2017/0147528 MANY-CORE PROCESSOR SYSTEM INTEGRATED WITH NETWORK ROUTER, AND INTEGRATION METHOD AND IMPLEMENTATION METHOD THEREOF
The present invention discloses a method for integrating a many-core processor system with a network router. The method comprises a subnet division step used...
2017/0147527 ACCESSING SHARED CONTENT USING COLLABORATION ATTRIBUTE PARTITIONING
Systems for managing shared content in a cloud-based service platform. A method commences upon identifying one or more storage devices that store one or more...
2017/0147526 Service Redirect Over USB Type-C
A service redirect operation mode allows a tester device to perform software burn-in, firmware upgrade, and other related device interrogation via a USB Type-C...
2017/0147525 DETERMINING CABLE CONNECTIONS IN A MULTI-CABLE LINK
A method for determining cable connections identifies a plurality of cables connected to a link included in a first device. The method identifies a first cable...
2017/0147524 INPUT/OUTPUT SWITCHING METHOD, ELECTRONIC DEVICE, AND SYSTEM FOR A SERVER
An input/output switching system for a server is disclosed herein. The input/output switching system includes a logic-determination device and at least one...
2017/0147523 ROUTING APPARATUS AND ROUTING METHOD AND COMPUTER SYSTEM AND PROGRAM AND STORAGE MEDIUM STORING PROGRAM
A technique is realized that provides a routing operation while using a Point-to-Point communication method as in PCI-Express. A routing address is inserted to...
2017/0147522 SYSTEMS AND METHODS FOR FLIPPING NIC TEAMING CONFIGURATION WITHOUT INTERFERING LIVE TRAFFIC
Systems and methods described herein facilitate configuration changes to an NIC teaming device while enabling multiple I/O threads continue to run through the...
2017/0147521 FULL-MASK PARTIAL-BIT-FIELD (FM-PBF) TECHNIQUE FOR LATENCY SENSITIVE MASKED-WRITE
Systems, methods, and apparatus for data communication are provided. An apparatus maybe configured to generate a mask field in a packet to be transmitted...
2017/0147520 ORTHOGONAL DIFFERENTIAL VECTOR SIGNALING CODES WITH EMBEDDED CLOCK
Orthogonal differential vector signaling codes are described which support encoded subchannels allowing transport of distinct data and clocking signals over...
2017/0147519 TRACKING STATISTICS CORRESPONDING TO DATA ACCESS IN A COMPUTER SYSTEM
Embodiments of the present invention disclose a method, computer program product, and system for determining statistics corresponding to data transfer...
2017/0147518 SCANNING MEMORY FOR DE-DUPLICATION USING RDMA
A method for storage includes storing multiple memory pages in a memory of a first compute node. Using a second compute node that communicates with the first...
2017/0147517 DIRECT MEMORY ACCESS SYSTEM USING AVAILABLE DESCRIPTOR MECHANISM AND/OR PRE-FETCH MECHANISM AND ASSOCIATED...
A direct memory access (DMA) system is implemented in an electronic device that communicates with a host device via a communication bus, and includes an...
2017/0147516 DIRECT INTERFACE BETWEEN GRAPHICS PROCESSING UNIT AND DATA STORAGE UNIT
A system is described that includes a data bus communicatively coupled to a host processor, a graphics processing unit (GPU), and a data storage unit. The GPU...
2017/0147515 ANTI-KEYLOG EDITOR
Various embodiments for protecting keyboard data inputted by a user in a computer having a keyboard hardware are disclosed. According to one exemplary...
2017/0147514 MEMORY MODULE WITH TIMING-CONTROLLED DATA PATHS IN DISTRIBUTED DATA BUFFERS
A memory module is operatable in a memory system with a memory controller. The memory module comprises a module control device mounted on the module board to...
2017/0147513 MULTIPLE PROCESSOR ACCESS TO SHARED PROGRAM MEMORY
A shared program memory and related components configured to distribute data from a memory block to multiple processors at the same time. An arbiter determines...
2017/0147512 SYSTEM AND METHOD FOR LOGICAL DELETION OF STORED DATA OBJECTS
Systems and methods for providing object versioning in a storage system may support the logical deletion of stored objects. In response to a delete operation...
2017/0147511 VIRTUAL MACHINE MEMORY LOCK-DOWN
A hypervisor receives, from a guest virtual machine, a request to disable access to a memory range. The hypervisor disables access to the memory range. The...
2017/0147510 SYSTEM AND METHOD FOR DETERRING MALICIOUS NETWORK ATTACKS
A system and method for deterring malicious network attacks. The system and method is configured to execute instructions on at least one of the processors to...
2017/0147509 Dynamic Memory Scrambling
A memory, a data processing system comprising a memory, a method of operating a memory and a memory compiler apparatus and method of memory compilation are...
2017/0147508 DEVICE, SYSTEM AND METHOD OF ACCESSING DATA STORED IN A MEMORY
Methods and systems are provided for accessing data stored in a memory. An example system may comprise a memory and one or more control circuits for managing...
2017/0147507 DIRECT MEMORY ACCESS OF DYNAMICALLY ALLOCATED MEMORY
Method and apparatus for direct memory access of dynamically allocated memory. The apparatus includes: a state receiving module operable to receive a...
2017/0147506 MULTI-CORE SHARED PAGE MISS HANDLER
Methods and apparatus are disclosed for using a shared page miss handler device to satisfy page miss requests of a plurality of devices in a multi-core system....
2017/0147505 SYSTEM AND METHODS EXCHANGING DATA BETWEEN PROCESSORS THROUGH CONCURRENT SHARED MEMORY
A method and apparatus for matching parent processor address translations to media processors' address translations and providing concurrent memory access to a...
2017/0147504 DATA STORAGE DEVICE AND DATA STORAGE METHOD
A data storage device utilized for storing at least one data includes a memory and a controller. The memory includes a plurality of blocks, and each of the...
2017/0147503 MEMORY SYSTEM AND OPERATING METHOD THEREOF
A memory system includes a memory device including first and second storage regions, each comprising a plurality of memory blocks and a controller suitable for...
2017/0147502 MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM
This technology relates to a memory system for processing data into a memory device and an operating method of the same. The memory system may include a memory...
2017/0147501 POST-COPY VM MIGRATION SPEEDUP USING FREE PAGE HINTING
A system and methods for migrating a virtual machine (VM). In one embodiment, a hypervisor receives a request to migrate the contents of a memory of a source...
2017/0147500 OPTIMIZING PAGE TABLE MANIPULATIONS
A computer program product for optimizing page table manipulations is provided and includes a computer readable storage medium having program instructions that...
2017/0147499 Multi-Level Logical to Physical Address Mapping Using Distributed Processors in Non-Volatile Storage Device
In a method to provide scalable and distributed address mapping in a storage device, a host command that specifies an operation to be performed and a logical...
2017/0147498 SYSTEM AND METHOD FOR UPDATING AN INSTRUCTION CACHE FOLLOWING A BRANCH INSTRUCTION IN A SEMICONDUCTOR DEVICE
A semiconductor device includes a memory for storing a plurality of instructions therein, an instruction queue which temporarily stores the instructions...
2017/0147496 Instruction And Logic For Cache Control Operations
In one embodiment, a processor includes: a fetch logic to fetch instructions; a decode logic to decode the instructions; a cache memory; and a control logic to...
2017/0147495 OPTIMIZED MEMORY LAYOUT THROUGH DATA MINING
A method of ordering memory access by an instruction cache of a central processing unit on a global memory device. A signal list of a link map file is...
2017/0147494 ALLOCATE A SEGMENT OF A BUFFER TO EACH OF A PLURALITY OF THREADS TO USE FOR WRITING DATA
Provided are a computer program product, system, and method to allocate a segment of a buffer to each of a plurality of threads to use for writing data. Each...
2017/0147493 PREFETCH CONFIDENCE AND PHASE PREDICTION FOR IMPROVING PREFETCH PERFORMANCE IN BANDWIDTH CONSTRAINED SCENARIOS
Techniques are disclosed for identifying data streams in a processor that are likely to benefit from data prefetching. A prefetcher receives at least a first...
2017/0147492 Method and System for Implementing Directory Structure of Host System
A method and system for implementing a directory structure of a host system are disclosed. The method includes: multiple basic computing units interconnecting...
2017/0147491 METHOD AND APPARATUS FOR DATA CACHE IN CONVERGED SYSTEM
A computer device including a node having a storage device having a plurality of first internal address spaces, a cache memory, and a processor may be...
2017/0147490 MEMORY CARD WITH VOLATILE AND NON VOLATILE MEMORY SPACE HAVING MULTIPLE USAGE MODEL CONFIGURATIONS
An apparatus is described that includes a memory card. The memory card also includes volatile memory devices. The memory card also includes non volatile memory...
2017/0147489 MEMORY SYSTEM AND OPERATING METHOD THEREOF
A memory system may include: a first memory device including a first normal block and a first auxiliary block; a second memory device including a second normal...
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