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Patent # Description
2017/0186733 Method for Aligning Micro-Electronic Components
Alignment of a first micro-electronic component to a receiving surface of a second micro-electronic component is realized by a capillary force-induced...
2017/0186731 SOLID STATE DRIVE OPTIMIZED FOR WAFERS
An SSD with a package optimized for semiconductor wafers is configured by thinning a plurality of undiced wafers and stacking the wafers. The wafers are...
2017/0186730 SYSTEM AND METHOD FOR PROVIDING 3D WAFER ASSEMBLY WITH KNOWN-GOOD-DIES
Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and...
2017/0186729 STACKED SEMICONDUCTOR DIES WITH SELECTIVE CAPILLARY UNDER FILL
Stacked semiconductor dies are provided with selective capillary under fill to avoid wafer warpage during curing. In one embodiment, a method of manufacturing...
2017/0186728 CHIP STACK COOLING STRUCTURE
An apparatus comprises a first die, a thermal cooler formed over at least a portion of the first die, a second die formed over at least a portion of the...
2017/0186727 DISCRETE FLEXIBLE INTERCONNECTS FOR MODULES OF INTEGRATED CIRCUITS
Flexible interconnects, flexible integrated circuit systems and devices, and methods of making and using flexible integrated circuitry are presented herein. A...
2017/0186726 Packaged Semiconductor Devices and Packaging Methods
Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an...
2017/0186725 SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND SEMICONDUCTOR WAFER
A semiconductor device manufacturing method improves the yield of manufacturing semiconductor devices. There are provided an insulating film for covering...
2017/0186724 SYSTEMS AND METHODS FOR BONDING SEMICONDUCTOR ELEMENTS
A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first...
2017/0186723 Trace Design for Bump-on-Trace (BOT) Assembly
A bump-on-trace (BOT) interconnection in a package and methods of making the BOT interconnection are provided. An embodiment BOT interconnection comprises a...
2017/0186722 SYSTEMS AND PROCESSES FOR MEASURING THICKNESS VALUES OF SEMICONDUCTOR SUBSTRATES
A system for determining thickness variation values of a semiconductor substrate comprises a substrate vacuumed to a pedestal that defines a reference plane...
2017/0186721 SEMICONDUCTOR MOUNTING APPARATUS, HEAD THEREOF, AND METHOD FOR MANUFACTURING LAMINATED CHIP
A semiconductor mounting apparatus includes a storing unit that stores a liquid or a gas, a contact unit that comes into contact with a semiconductor chip when...
2017/0186720 ADHESIVE BONDING COMPOSITION AND ELECTRONIC COMPONENTS PREPARED FROM THE SAME
A polymerizable composition includes at least one monomer, a photoinitiator capable of initiating polymerization of the monomer when exposed to light, and a...
2017/0186719 SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SAME, AND ELECTRONIC APPARATUS
A semiconductor device includes a first substrate, a second substrate, a connection portion, and resin. The second substrate faces the first substrate, and has...
2017/0186718 ELECTRONIC DEVICE, ELECTRONIC DEVICE FABRICATION METHOD, AND ELECTRONIC APPARATUS
An electronic device includes an electronic part including a first substrate having a group of first terminals over a first front surface and having a...
2017/0186717 METHOD AND STRUCTURE FOR WAFER-LEVEL PACKAGING
A method for wafer-level packaging includes providing a substrate having a conductive metal pad formed on the surface of the substrate; forming a metal core on...
2017/0186716 CHIP WITH I/O PADS ON PERIPHERIES AND METHOD MAKING THE SAME
A chip with I/O pads on the peripheries and a method making the chip is disclosed. The chip includes: a substrate; a first metal layer, formed above the...
2017/0186715 Bond Structures and the Methods of Forming the Same
A method includes forming a first conductive feature and a second conductive feature, forming a metal pad over and electrically connected to the first...
2017/0186714 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A semiconductor device of the present invention includes a semiconductor element, a surface electrode formed on a surface of the semiconductor element, a metal...
2017/0186713 SYSTEM AND METHOD FOR AN IMPROVED INTERCONNECT STRUCTURE
Presented herein are an interconnect structure and method for forming the same. The interconnect structure includes a contact pad disposed over a substrate and...
2017/0186712 CHIP PACKAGE AND METHOD FOR FORMING THE SAME
A chip package including a substrate is provided. The substrate includes a front surface, a back surface, and a side surface. A redistribution layer is...
2017/0186711 STRUCTURE AND METHOD OF FAN-OUT STACKED PACKAGES
A fan-out stacked packages are formed by stacking a plurality of tiers followed by singulation process. Each tier comprises a plurality of units. Each unit...
2017/0186710 GLASS INTERPOSER INTEGRATED HIGH QUALITY ELECTRONIC COMPONENTS AND SYSTEMS
Various integrated high quality electronic components and systems, and methods of their manufacture, are presented. In one example, a device includes a glass...
2017/0186709 MANUFACTURING METHOD OF CHIP PACKAGE AND PACKAGE SUBSTRATE
A manufacturing method of a package substrate is provided. The method includes forming a first circuit layer on a carrier. A passive component is disposed on...
2017/0186708 Electronic device packages with conformal emi shielding and related methos
Electronic device package technology is disclosed. In one example, an electronic device package can include a bottom surface and a side surface extending from...
2017/0186707 STRUCTURES TO MITIGATE CONTAMINATION ON A BACK SIDE OF A SEMICONDUCTOR SUBSTRATE
Techniques and mechanisms to mitigate contamination of redistribution layer structures disposed on a back side of a semiconductor substrate. In an embodiment,...
2017/0186706 SYSTEM AND METHOD FOR PROTECTING AN INTEGRATED CIRCUIT (IC) DEVICE
Embodiments of the invention provide a system for protecting an integrated circuit (IC) device from attacks, the IC device (100) comprising a substrate (102)...
2017/0186705 Non-Rectangular Electronic Device Components
Electronic device shape configuration technology is disclosed. In an example, an electronic device substrate is provided that can comprise a top surface, and a...
2017/0186704 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING MOISTURE-RESISTANT RINGS BEING FORMED IN A PERIPHERAL REGION
A semiconductor device includes a first moisture-resistant ring disposed in a peripheral region surrounding a circuit region on a semiconductor substrate in...
2017/0186702 PACKAGING SUBSTRATE AND ELECTRONIC PACKAGE HAVING THE SAME
A packaging substrate is provided, which includes: a substrate body having a first region with a plurality of conductive pads and a second region adjacent to...
2017/0186701 CRACK RESISTANT ELECTRONIC DEVICE PACKAGE SUBSTRATES
Crack resistant electronic device package substrate technology is disclosed. In an example, an electronic device package substrate can include a substrate core...
2017/0186700 SEMICONDUCTOR PACKAGE STRUCTURE BASED ON CASCADE CIRCUITS
A semiconductor package structure comprises: a high-voltage depletion type semiconductor transistor comprising a source electrode, a gate electrode and a drain...
2017/0186699 Electromagnetic interference shielding for system-in-package technology
Embodiments are generally directed to electromagnetic interference shielding for system-in-package technology. An embodiment of a system-in-package includes a...
2017/0186698 ELECTRONIC PACKAGE HAVING ELECTROMAGNETIC INTERFERENCE SHIELDING AND ASSOCIATED METHOD
An electronic package includes a substrate having opposing first and second surfaces. Conductive areas are on a first surface of the substrate and include at...
2017/0186697 Electromagnetically shielded electronic devices and related systems and methods
Electromagnetically shielded electronic device technology is disclosed. In an example, a method of making an electronic device package can comprise providing a...
2017/0186696 METHOD OF MARKING A SEMICONDUCTOR PACKAGE
A method of making a semiconductor device can include providing a wafer comprising a plurality of semiconductor die, wherein each semiconductor die comprises...
2017/0186695 Method of Manufacturing a Semiconductor Device with Epitaxial Layers and an Alignment Mark
An alignment mark in a process surface of a semiconductor layer includes a groove with a minimum width of at least 100 .mu.m and a vertical extension in a...
2017/0186694 DEVICES AND METHODS RELATED TO A SPUTTERED TITANIUM TUNGSTEN LAYER FORMED OVER A COPPER INTERCONNECT STACK...
Disclosed are devices and methods related to metallization of semiconductors. A metalized structure can include a stack disposed over a compound semiconductor,...
2017/0186693 SOI WAFERS WITH BURIED DIELECTRIC LAYERS TO PREVENT CU DIFFUSION
An SOI semiconductor device includes a first wafer having an active semiconductor layer and a first oxide layer and a second wafer having a semiconductor...
2017/0186692 METAL GATE TRANSISTOR AND FABRICATION METHOD THEREOF
A method for fabricating a metal gate transistor includes forming a dummy gate structure surrounded by a first dielectric layer on a semiconductor substrate...
2017/0186691 TECHNIQUES BASED ON ELECTROMIGRATION CHARACTERISTICS OF CELL INTERCONNECT
In some embodiments, the present disclosure relates to a clock tree structure disposed on a semiconductor substrate. The clock tree structure includes a first...
2017/0186690 Semiconductor Device and Method of Forming Inductor Over Insulating Material Filled Trench in Substrate
A semiconductor device has a trench formed in a substrate. The trench has tapered sidewalls and depth of 10-120 micrometers. A first insulating layer is...
2017/0186689 SENSOR DEVICE
A sensor device includes a power line and a semiconductor device. The semiconductor device includes an inductor. The inductor is formed using an interconnect...
2017/0186688 METHODS AND DEVICES FOR METAL FILLING PROCESSES
Metal filling processes for semiconductor devices and methods of fabricating semiconductor devices. One method includes, for instance: obtaining a wafer with...
2017/0186687 METHOD FOR SELECTIVE RE-ROUTING OF SELECTED AREAS IN A TARGET LAYER AND IN ADJACENT INTERCONNECTING LAYERS OF...
Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are...
2017/0186686 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a plurality of lower conductive lines overlying a substrate and extending in a first direction, an insulating layer overlying...
2017/0186685 Method of Forming Metal Interconnection
A device includes a first conductive feature disposed over a substrate; a second conductive feature disposed directly on and in physical contact with the first...
2017/0186684 WIRING SUBSTRATE
A wiring substrate includes a first insulation layer, a wiring layer formed on an upper surface of the first insulation layer, a barrier film that covers the...
2017/0186683 Method and Structure for Interconnection
The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes forming a first...
2017/0186682 SELF-ALIGNED VIA FORMING TO CONDUCTIVE LINE AND RELATED WIRING STRUCTURE
A method of forming a via and a wiring structure formed are disclosed. The method may include forming a conductive line in a first dielectric layer; forming a...
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