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Patent # Description
2017/0186681 Packaging Device Having Plural Microstructures Disposed Proximate to Die Mounting Region
An example method includes providing a packaging device includes a substrate having an integrated circuit die mounting region. A plurality of microstructures,...
2017/0186680 WIRING SUBSTRATE
[Object] To provide a Wiring substrate in which, even if, for example, a front surface of a ceramic substrate body is provided with an electrically independent...
2017/0186679 Semiconductor Device Package and Manufacturing Method Thereof
Methods and systems for a semiconductor device package with a die to interposer wafer first bond are disclosed and may include bonding a plurality of...
2017/0186678 FAN-OUT CHIP PACKAGE AND ITS FABRICATING METHOD
A fan-out chip package comprises a chip, an encapsulating layer, a first passivation layer, a redistribution wiring layer, a second passivation layer, and a...
2017/0186677 WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE
A wiring substrate includes a first wiring layer that is an uppermost wiring layer, a protective insulation layer that covers the first wiring layer, and a...
2017/0186676 SEMICONDUCTOR PACKAGE
A semiconductor package is provided. In one configuration, the semiconductor package includes a substrate having a die attach surface. A conductive trace is...
2017/0186675 POWER SEMICONDUCTOR DEVICE WITH SMALL CONTACT FOOTPRINT AND THE PREPARATION METHOD
A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and...
2017/0186674 SEMICONDUCTOR PACKAGES AND METHODS FOR FORMING SAME
One or more embodiments are directed to a semiconductor package that includes an integrated heatsink and methods of forming same. In one embodiment, the...
2017/0186673 POWER SEMICONDUCTOR ARRANGEMENT
A power semiconductor device comprises a substrate; and power semiconductor components disposed on and connected thereto. The device includes a housing part...
2017/0186672 ELECTRONIC ELEMENT MOUNTING SUBSTRATE AND ELECTRONIC DEVICE
An electronic element mounting substrate includes: a first wiring substrate configured to be a frame defining an interior portion as a first through-hole, the...
2017/0186671 BIPOLAR TRANSISTOR, SEMICONDUCTOR DEVICE, AND BIPOLAR TRANSISTOR MANUFACTURING METHOD
Disconnection of a base line is suppressed even when a short-side direction of a collector layer is parallel to crystal orientation [011]. A bipolar transistor...
2017/0186670 PACKAGING OPTOELECTRONIC COMPONENTS AND CMOS CIRCUITRY USING SILICON-ON-INSULATOR SUBSTRATES FOR PHOTONICS...
Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For...
2017/0186669 PROCESS FLOW FOR A COMBINED CA AND TSV OXIDE DEPOSITION
A method of forming a TSV isolation layer and a transistor-to-BEOL isolation layer during a single deposition process and the resulting device are disclosed....
2017/0186668 SEMICONDUCTOR DEVICE WITH THROGH-SUBSTRATE VIA AND METHOD FOR FABRICATION THE SEMICONDUCTOR DEVICE
A method for is used for forming a semiconductor device having a through-substrate via. The method includes providing a preliminary structure having an ILD...
2017/0186667 COOLING OF ELECTRONICS USING FOLDED FOIL MICROCHANNELS
Embodiments are generally directed to cooling of electronics using folded foil microchannels. An embodiment of an apparatus includes a semiconductor die; a...
2017/0186666 FLEXIBLE MODULAR HIERARCHICAL ADAPTIVELY CONTROLLED ELECTRONIC-SYSTEM COOLING AND ENERGY HARVESTING FOR IC CHIP...
A system for adaptive cooling and energy harvesting comprising at least one thermoelectric device capable of acting as a thermoelectric cooler and as a...
2017/0186665 Multi-reference integrated heat spreader (IHS) solution
Methods, systems, and apparatuses that assist with cooling semiconductor packages, such as multi-chip packages (MCPs) are described. A semiconductor package...
2017/0186664 HEAT DISSIPATION MATERIAL AND METHOD OF MANUFACTURING THEREOF, AND ELECTRONIC DEVICE AND METHOD OF...
A heat dissipation material includes a plurality of linearly-structured objects of carbon atoms configured to include a first terminal part and a second...
2017/0186663 Semiconductor Device Including a Heat Sink Structure
A semiconductor device includes a drift structure formed in a semiconductor body. The drift structure forms a first pn junction with a body zone of a...
2017/0186662 APPLYING PHASE SEPARATION OF A SOLVENT MIXTURE WITH A LOWER CRITICAL SOLUTION TEMPERATURE FOR ENHANCEMENT OF...
A method and system for cooling a device (preferably a micro-device), comprising cooling the device by using a lower critical solution temperature (LCST)...
2017/0186661 Rework grid array interposer with direct power
A rework grid array interposer with direct power is described. The interposer has a foundation layer mountable between a motherboard and a package. A heater is...
2017/0186660 Semiconductor Device and Method of Forming Ultra High Density Embedded Semiconductor Die Package
A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer...
2017/0186659 SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES AND METHODS OF MANUFACTURING THE SAME
Semiconductor devices are provided. The semiconductor device includes a semiconductor layer having a first surface and a second surface that are opposite each...
2017/0186658 Mold compound with reinforced fibers
Techniques and mechanisms for mitigating warpage of structures in a package. In an embodiment, a packaged integrated circuit device includes a mold compound...
2017/0186657 SEMICONDUCTOR DEVICE
Provided is a semiconductor device including an insulating substrate on which a semiconductor chip is mounted and a case that is adhered to the insulating...
2017/0186656 WAFER PROCESSING METHOD
Disclosed herein is a wafer processing method including a processed position measuring step of imaging an area including a beam plasma generated by applying a...
2017/0186655 Structure for Die Probing
A package includes a device die, which includes a metal pillar at a top surface of the device die, and a solder region on a sidewall of the metal pillar. A...
2017/0186654 FIN-FET DEVICE AND FABRICATION METHOD THEREOF
A method for fabricating a Fin-FET device includes forming fin structures with each having a gate structure on the top in both P-type regions and N-type...
2017/0186653 FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE
A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a semiconductor substrate and forming a dummy...
2017/0186652 METHOD FOR PREVENTING DISHING DURING THE MANUFACTURE OF SEMICONDUCTOR DEVICES
A method for manufacturing a semiconductor device and a device manufactured using the same are provided. According to a method approach of the embodiment, a...
2017/0186651 ARRAY SUBSTRATE AND MANUFACTURING METHOD FOR THE SAME
An array substrate and a manufacturing method therefor. The method comprises: patterning a first metal layer by means of a first photomask so as to form a gate...
2017/0186650 Replacement Gate Process for Semiconductor Devices
Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and gate stacks over the substrate,...
2017/0186649 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device manufacturing method includes forming a silicon layer by epitaxial growth over a semiconductor substrate having a first area and a...
2017/0186647 METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE
In some embodiments, a semiconductor structure includes a first device and a second device. The first device has a first surface. The first device includes a...
2017/0186646 WAFER PROCESSING METHOD
A wafer processing method including the steps of storing information on the intervals and positions of metal patterns formed on part of division lines on a...
2017/0186645 METHOD OF PROCESSING WAFER
A wafer has a plurality of projected dicing lines on a face side thereof, a plurality of devices formed in respective areas demarcated on the face side of the...
2017/0186644 METHOD FOR MAKING AN INTEGRATED CIRCUIT (IC) PACKAGE WITH AN ELECTRICALLY CONDUCTIVE SHIELD LAYER
A method for making at least one integrated circuit (IC) package includes positioning an electrically conductive shield layer adjacent an interior of a mold,...
2017/0186643 DEVICE LAYER TRANSFER WITH A PRESERVED HANDLE WAFER SECTION
Assemblies including a device layer of a silicon-on-insulator (SOI) substrate and a replacement substrate replacing a handle wafer of the SOI substrate, and...
2017/0186642 ISOLATION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A method for manufacturing a semiconductor device includes forming a first trench and a second trench in a substrate, the first and the second trenches...
2017/0186641 MOUNTING MEMBER
A mounting member includes a body having a surface including a mounting surface on which an object is mountable, a channel arranged in the body, and a first...
2017/0186640 POSITIONING DEVICE FOR GLASS SUBSTRATE
The present invention provides a positioning device configured to position a glass substrate. The positioning device comprises a support base, a pair of first...
2017/0186639 CARRIER BUFFERING DEVICE AND BUFFERING METHOD
A temporary storage apparatus is provided with a slidable buffer which does not prevent installation of the apparatus and maintenance of equipment, has...
2017/0186637 WAFER CONTAINER FOR RECEIVING HORIZONTALLY ARRANGED WAFERS
A wafer container includes a base, a guide, a cover, a locking member and a sealing member. The base includes an installing surface thereon. The guide is...
2017/0186636 TRAY FOR SEMICONDUCTOR DEVICES
A tray for semiconductor devices includes a base with a positioning unit. The positioning unit includes a plurality of tiered projections which jointly define...
2017/0186635 CHIP ACCOMMODATION TRAY
A chip accommodation tray for accommodating a plurality of chips includes a holding sheet for holding the chips on a face side thereof, the holding sheet...
2017/0186634 SUBSTRATE PROCESSING APPARATUS
A substrate processing apparatus, including: a process chamber configured to process a substrate, a transfer chamber adjoining the process chamber, a shaft...
2017/0186633 SUBSTRATE PROCESSING SYSTEM
A substrate processing system includes a first chamber, a second chamber, a gas control part for controlling a gas flow in at least one of the chambers, a gate...
2017/0186632 IMMERSION DE-TAPING
Embodiments using immersion de-taping are described. A substrate having a substrate tape attached thereto is provided. The substrate includes electrically...
2017/0186631 APPARATUS AND METHOD FOR REDUCING SUBSTRATE SLIDING IN PROCESS CHAMBERS
Methods and apparatus for processing a substrate are disclosed herein. In some embodiments, an apparatus for processing a substrate includes: a substrate...
2017/0186630 SUBSTRATE MACHINING APPARATUS
The present invention discloses a substrate machining apparatus, which comprises a clamping means for clamping the substrate and a supporting means for...
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