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Patent # Description
2017/0206989 In-Containment Ex-Core Detector System
Apparatus for amplifying low level signals within a nuclear plant's containment building, derived from the ex-core nuclear instrumentation system. The system...
2017/0206988 THERMOACOUSTIC ENHANCEMENTS FOR NUCLEAR FUEL RODS AND OTHER HIGH TEMPERATURE APPLICATIONS
A nuclear thermoacoustic device includes a housing defining an interior chamber and a portion of nuclear fuel disposed in the interior chamber. A stack is...
2017/0206986 CONVECTIVE DRY FILTERED CONTAINMENT VENTING SYSTEM
A dry FCVS for a nuclear reactor containment is provided. The dry FCVS includes a housing and a round and/or elongated aerosol filter inside the housing for...
2017/0206985 TOP NOZZLE AND PRESSURIZED WATER NUCLEAR REACTOR INCLUDING SAME
The present invention provides a top nozzle for use with PWR nuclear reactors and power plants, and in particular, VVER nuclear reactors. The top nozzle...
2017/0206984 END CAP FOR NUCLEAR FUEL ROD HAVING AN ANGLED RECESS AND WELDING THEREOF
An end cap for a nuclear fuel rod and methods of welding the end cap to a cladding tube, particularly an HT9 end cap to an HT9 cladding tube, such as by...
2017/0206983 METHOD AND FUEL DESIGN TO STABILIZE BOILING WATER REACTORS
A method of stabilizing density wave oscillations in boiling water reactor cores is disclosed. The invention introduced a thin metallic fuel element made of...
2017/0206982 MEMORY DEVICE AND METHOD FOR TESTING A MEMORY DEVICE
According to one embodiment, a memory device is provided including a plurality of data word memories, a test controller configured to, for each data word...
2017/0206981 FEEDBACK VALIDATION OF ARBITRARY NON-VOLATILE MEMORY DATA
An integrated circuit and method of performing a reliability screen of an electrically programmable non-volatile memory array in the integrated circuit. At a...
2017/0206980 METHOD FOR PROGRAMMING ANTIFUSE-TYPE ONE TIME PROGRAMMABLE MEMORY CELL
A method for programming an antifuse-type OTP memory cell is provided. Firstly, a first program voltage is provided to a gate terminal of an antifuse...
2017/0206979 RETENTION-DRIFT-HISTORY-BASED NON-VOLATILE MEMORY READ THRESHOLD OPTIMIZATION
Methods, systems and computer-readable storage media for selecting a retention drift predictor scheme, reading retention drift history associated with...
2017/0206978 FLASH MEMORY DEVICE REVISING PROGRAM VOLTAGE, THREE-DIMENSIONAL MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE...
A method of programming a flash memory device, which is a nonvolatile memory device including a plurality of pages, includes executing an N.sup.th program loop...
2017/0206977 MEMORY DEVICES THAT APPLY A PROGRAMMING POTENTIAL TO A MEMORY CELL IN A STRING COUPLED TO A SOURCE AND DATA...
A first string of memory cells, including a selected memory cell, and a second string of memory cells are coupled to a common data line and a common source....
2017/0206976 POWER SWITCH CIRCUIT
A power switch circuit includes a first transistor, a second transistor and a current source. A first source/drain terminal and a gate terminal of the first...
2017/0206974 STORAGE SYSTEM, HOST, STORAGE DEVICE, AND METHODS OF OPERATING SAME
A storage device includes a nonvolatile memory and a connector configured to connect the storage device to a host. The connector includes a detection terminal...
2017/0206973 SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF
A NADN flash memory suppresses an influence caused by FG coupling and has high reliability. The flash memory of the invention includes: a memory array formed...
2017/0206972 LATCH CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE
A latch circuit provided herein includes an input circuit including a PMOS transistor that is configured for input and enables a signal current to flow into...
2017/0206971 SEMICONDUCTOR DEVICE
A semiconductor device includes a first memory mat (1L) including a plurality of split type memory cells (250L), a second memory mat (1R) including a plurality...
2017/0206970 MEMORY ARRAY CAPABLE OF PERFORMING BYTE ERASE OPERATION
A memory array includes a plurality of memory pages, each memory page includes a plurality of memory bytes, each memory byte includes a plurality of memory...
2017/0206969 MEMORY CELL WITH HIGH ENDURANCE FOR MULTIPLE PROGRAM OPERATIONS
A memory cell includes a read transistor, a first floating gate transistor, a program transistor, a second floating gate transistor, and a common floating...
2017/0206968 MEMORY ARRAY WITH ONE SHARED DEEP DOPED REGION
A memory array includes a plurality of memory pages, each memory page includes a plurality of memory cells, and each memory cell includes a floating gate...
2017/0206967 FUNCTIONAL DATA PROGRAMMING IN A NON-VOLATILE MEMORY
Methods of operating a memory include receiving a plurality of digits of data, determining a value of the plurality of digits of data, and selecting a function...
2017/0206966 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
In an embodiment, a method of operating a semiconductor memory device may include performing a read operation on a selected memory block, and, during the read...
2017/0206964 Integrated Circuitry and 3D Memory
Integrated circuitry comprises an array circuitry region comprising a repeating array of electronic components. An adjacent circuitry region is immediately...
2017/0206963 CIRCUIT AND METHOD FOR CONFIGURABLE IMPEDANCE ARRAY
A configurable impeder is provided. The configurable impeder comprises of multiple CESs. Each of the CESs is capable of being configured into one of a...
2017/0206962 MEMRISTOR PROGRAMMING ERROR REDUCTION
Error reduction in memristor programming includes programming an n-th switched memristor of a switched memristor array with an error-corrected target...
2017/0206961 ELECTRONIC DEVICE AND METHOD FOR DRIVING THE SAME
An electronic device including a semiconductor memory may be provided. The semiconductor memory may include a write circuit configured for generating a first...
2017/0206960 MEMORY DEVICE AND OPERATING METHOD FOR RESISTIVE MEMORY CELL
A memory device and an operating method for a resistive memory cell are provided. The memory device includes the resistive memory cell. The resistive memory...
2017/0206959 CROSSBAR ARRAYS WITH SHARED DRIVERS
A crossbar array with shared drivers has a plurality of sets of row lines, a set of row drivers, a plurality of sets of column lines, a set of column drivers,...
2017/0206958 CIRCUIT AND ARRAY CIRCUIT FOR IMPLEMENTING SHIFT OPERATION
A circuit and an array circuit for implementing a shift operation are provided. The circuit for implementing a shift operation includes a resistive...
2017/0206957 SENSING AN OUTPUT SIGNAL IN A CROSSBAR ARRAY
A method of sensing an output signal in a crossbar array is described. In the method, a selecting voltage is applied to a target memory element of the crossbar...
2017/0206956 SENSING CIRCUIT FOR RESISTIVE MEMORY
This disclosure provides a circuit that includes a ramp generator to apply a voltage ramp to a resistive memory cell. A sensing circuit can enable the ramp...
2017/0206955 MEMRISTOR CELL READ MARGIN ENHANCEMENT
Memristor cell read margin enhancement employs programming switched memristor sub-bits of a memristor cell with a first resistive state to increase a relative...
2017/0206954 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TEMPERATURE COMPENSATION USING TEMPERATURE-RESISTANCE-VOLTAGE FUNCTIONS
A semiconductor device includes: a physical parameter sensing circuit configured to sense a variation of a physical parameter; an applying parameter generating...
2017/0206953 NON-VOLATILE MEMORY APPARATUS AND ON-THE-FLY SELF-ADAPTIVE READ VOLTAGE ADJUSTMENT METHOD THEREOF
A non-volatile memory apparatus includes a non-volatile storage circuit and a controller. The non-volatile storage circuit reads a corresponding data voltage...
2017/0206951 Semiconductor Device
A logic circuit in a system LSI is provided with a power switch so as to cut off the switch at the time of standby, reducing leakage current. At the same time,...
2017/0206950 HIGH RELIABILITY STATIC RANDOM-ACCESS MEMORY CELL
An SRAM cell includes a write inverter including a write pull-up transistor and a write pull-down transistor, a read inverter including a read pull-up...
2017/0206949 MEMORY UNIT
There is provided a memory unit (100). The memory unit comprises a plurality of memory cells (110), each memory cell of the plurality of memory cells being...
2017/0206948 Encoded Global Bitlines for Memory and Other Circuits
Encoded bitlines run globally through a memory architecture. The encoded bitlines carry an encoded representation of the data bits read from memory cells. As a...
2017/0206947 AUTOMATIC DELAY-LINE CALIBRATION USING A REPLICA ARRAY
A computer memory system, delay calibration circuit, and method of operating a delay calibration circuit are provided. The disclosed method includes providing...
2017/0206946 SELF-TIMED RESET PULSE GENERATOR AND MEMORY DEVICE WITH SELF-TIMED RESET PULSE GENERATOR
A self-timed reset pulse generator includes a flip-flop, a tracking block, and a tracking circuit. The flip-flop receives an input signal and a feedback signal...
2017/0206945 MEMORY DEVICE, PERIPHERAL CIRCUIT THEREOF AND SINGLE-BYTE DATA WRITE METHOD THEREOF
A memory device, a peripheral circuit thereof and a single-byte data write method thereof are provided. The peripheral circuit includes a Y decoder, a page...
2017/0206944 BITLINE SENSEAMPLIFIER AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME
A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and...
2017/0206943 BITLINE SENSEAMPLIFIER AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME
A memory apparatus may include a bit line sense-amplifier coupled to first and second bit lines; a first precharge unit suitable for coupling the first and...
2017/0206941 DRIVING CIRCUIT FOR NON-VOLATILE MEMORY
A driving circuit includes a driving stage with a first level shifter and a second level shifter. The first level shifter includes an input terminal receiving...
2017/0206940 SEMICONDUCTOR DEVICE
A semiconductor device may be provided. The semiconductor device may include a first chip and a second chip. The second chip may be configured to receive...
2017/0206939 Programmable Logic Accelerator in System on Chip
A programmable logic array (PLA) is disclosed employing programming logic tile (PLT), System On Chip (SOC) interface bus, Input Output (IO) blocks and Logic...
2017/0206938 DUAL-BIT 3-T HIGH DENSITY MTPROM ARRAY
A multi-time programmable memory (MTPM) memory cell and method of operating. Each MTPM bit cell including a first FET transistor and a second FET transistor...
2017/0206937 HYBRID SYSTEM INTEGRATING PACKAGE-ON-PACKAGE SOC AND EMBEDDED MULTI-CHIP PACKAGE ON ONE MAIN CIRCUIT BOARD
A hybrid system includes a printed circuit board (PCB) having a main surface, a package-on-package (PoP) having a bottom package mounted on the main surface of...
2017/0206936 DISK DEVICE AND METHOD OF MANUFACTURING DISK DEVICE ENCLOSURE INCLUDING LASER WELDING A PERIPHERAL EDGE PORTION...
According to one embodiment, a disk device includes a rotatable disk-shaped recording medium, an actuator supporting a head to be movable with respect to the...
2017/0206935 METHOD AND ELECTRONIC APPARATUS FOR GENERATING TIME-LAPSE VIDEO AND RECORDING MEDIUM USING THE METHOD
A method and an electronic apparatus for generating a time-lapse video and a recording medium using the method are provided. In the method, a movement of the...
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