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Patent # Description
2017/0229393 SEMICONDUCTOR DEVICES
A semiconductor device includes a substrate and at least one inductor on the substrate. The inductor includes top portions separated from one another, bottom...
2017/0229392 Novel 3D Integration Method Using SOI Substrates and Structures Produced Thereby
A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon...
2017/0229390 INTERCONNECTION AND MANUFACTURING METHOD THEREOF
An interconnection and a method for manufacturing thereof are provided. The interconnection includes a first conductive layer, a dielectric layer, a second...
2017/0229389 SEMICONDUCTOR DEVICE
In a semiconductor device, a first end of a first lead frame is connected via solder to a first circuit pattern and another end extends outside from a case. In...
2017/0229388 WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE
A wiring substrate includes a core substrate and a cavity extending through the core substrate. The cavity has a planar shape that is rectangular, and includes...
2017/0229387 SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
A semiconductor package is provided, including a semiconductor substrate having a plurality of conductive vias, a buffer layer formed on the semiconductor...
2017/0229386 SUBSTRATE STRUCTURE
A substrate structure is provided, including a substrate body having a conductive pad, an insulation layer formed on the substrate body and exposing the...
2017/0229385 METHOD OF MANUFACTURING ELEMENT CHIP, METHOD OF MANUFACTURING ELECTRONIC COMPONENT-MOUNTED STRUCTURE, AND...
To provide a method of manufacturing an element chip in which creep-up of a conductive material can be suppressed in a mounting step. In a plasma processing...
2017/0229384 METHOD OF MANUFACTURING ELEMENT CHIP, METHOD OF MANUFACTURING ELECTRONIC COMPONENT-MOUNTED STRUCTURE, AND...
In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate...
2017/0229383 POWER QUAD FLAT NO-LEAD (PQFN) PACKAGE IN A SINGLE SHUNT INVERTER CIRCUIT
According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a driver integrated circuit (IC) situated on a leadframe. The PQFN...
2017/0229382 SEMICONDUCTOR DEVICE
A semiconductor device includes two or more semiconductor elements, a lead with island portions on which the semiconductor elements are mounted, a heat...
2017/0229381 THREE-DIMENSIONAL INTEGRATED CIRCUIT
Disclosed is a three-dimensional integrated circuit divided into a plurality of groups and capable of repairing failed through-silicon vias (TSVs). In...
2017/0229380 SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor substrate through which a via hole is formed from a back surface to a front surface of the semiconductor...
2017/0229379 INSULATED BUSBAR, INSULATED BUSBAR FABRICATION METHOD, AND ELECTRONIC APPARATUS
An insulated busbar includes a plate conductor and insulating films which cover the plate conductor. The insulated busbar further includes conductive films...
2017/0229378 INVERTER POWER MODULE PACKAGING WITH COLD PLATE
A heat sink is provided. The heat sink includes a single-piece housing having a floor and two walls, the walls perpendicular to the floor and the walls are...
2017/0229377 LIQUID MANIFOLD STRUCTURE FOR DIRECT COOLING OF LIDDED ELECTRONICS MODULES
Embodiments of the present invention provide efficient and cost-effective systems for a lidded electronic device. The lidded electronic device includes an...
2017/0229375 HEAT TRANSFER DEVICE FOR HIGH HEAT FLUX APPLICATIONS AND RELATED METHODS THEREOF
A device and related method that provides a two-phase heat transfer device with a combination of enhanced evaporation and increase cooling capacity. A recess...
2017/0229374 HEAT SINK WITH INTEGRATED THREADED LID
A method affixes a heat sink to a module lid. A module lid is mounted to a substrate by use of a lid adhesive. The module lid has a threaded exterior portion....
2017/0229373 THERMOELECTRIC COOLING PACKAGES AND THERMAL MANAGEMENT METHODS THEREOF
A method for managing a temperature of a device includes determining a temperature of a circuit or a package including the circuit, and selectively operating a...
2017/0229372 SEMICONDUCTOR DEVICE WITH INTERCONNECT STRUCTURE HAVING CATALYS LAYER
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a dielectric layer over the...
2017/0229371 ELECTRONIC DEVICE
An electronic device includes: a heating element; an insulation metal component; and a sealing component. The insulation metal component includes a first metal...
2017/0229370 Mechanically Stable, Thermally Conductive And Electrically Insulating Stack For Mounting Device
A mounting device for mounting electronic components, wherein the mounting device comprises a stack, in particular a layer stack configured as alternating...
2017/0229369 ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND FABRICATION METHOD THEREOF
An electrostatic discharge (ESD) protection device includes a substrate including a device region and an ESD protection structure formed on the substrate in...
2017/0229368 TOP-SIDE COOLING OF RF PRODUCTS IN AIR CAVITY COMPOSITE PACKAGES
Top-side cooling of Radio Frequency (RF) products in air cavity packages is provided. According to one aspect, an air cavity package comprises a substrate, a...
2017/0229367 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
The present disclosure provides semiconductor structures and fabrication methods thereof. An exemplary semiconductor structure includes an insulation material...
2017/0229366 METHOD OF MANUFACTURING ELEMENT CHIP AND ELEMENT CHIP
In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate...
2017/0229365 METHOD OF MANUFACTURING ELEMENT CHIP AND ELEMENT CHIP
In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate...
2017/0229364 FABRICATION METHOD OF SEMICONDUCTOR PACKAGE
A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the...
2017/0229363 CHIP PART AND METHOD OF MAKING THE SAME
A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing...
2017/0229362 CORROSION RESISTANT CHIP SIDEWALL CONNECTION WITH CRACKSTOP AND HERMETIC SEAL
The present disclosure relates to semiconductor structures and, more particularly, to corrosion resistant chip sidewall connections with crackstop structures...
2017/0229360 CERAMIC COMBO LID WITH SELECTIVE AND EDGE METALLIZATIONS
A frame lid for use with a semiconductor package is disclosed. First, a mask is applied to a top surface of the lid and over a central area of the top surface...
2017/0229359 SEMICONDUCTOR DEVICE WITH BOND PAD WIRING LEAD-OUT ARRANGEMENT AVOIDING BOND PAD PROBE MARK AREA
Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening...
2017/0229358 TEST STRUCUTRE FOR MONITORING INTERFACE DELAMINATION
Aspects of the present disclosure include a test structure that includes two or more devices. Each device includes a wire disposed within a dielectric and a...
2017/0229357 Method and System of Surface Polishing
A method of polishing a surface of an object disposed within a gas chamber is provided. The method includes filling the gas chamber with a discharging medium...
2017/0229356 ASSESSMENT METHOD, AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
To easily assess a feedback capacitance of a semiconductor element. An assessment method of assessing a feedback capacitance of a semiconductor element is...
2017/0229355 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING SEMICONDUCTOR CHIP MOUNTED ON LEAD FRAME
A semiconductor device uses a lead frame, in which an outer lead is electrically connected to an inner lead suspension lead via an inner lead. An encapsulating...
2017/0229354 CMOS IMPLEMENTATION OF GERMANIUM AND III-V NANOWIRES AND NANORIBBONS IN GATE-ALL-AROUND ARCHITECTURE
Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge)...
2017/0229353 Hybrid ETSOI Structure to Minimize Noise Coupling from TSV
In one aspect, a method for forming an electronic device includes the following steps. An ETSOI layer of an ETSOI wafer is patterned into one or more ETSOI...
2017/0229352 Fabricating a Dual Gate Stack of a CMOS Structure
A dual gate CMOS structure including a semiconductor substrate; a first channel structure including a first semiconductor material and a second channel...
2017/0229351 FIN PROFILE IMPROVEMENT FOR HIGH PERFORMANCE TRANSISTOR
A finFET semiconductor device and method for fabricating such a device are presented. The semiconductor device includes a first fin formed in a first...
2017/0229350 SINGLE SPACER FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR PROCESS FLOW
A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device...
2017/0229349 Self-Aligned Nanowire Formation Using Double Patterning
A method includes forming a pattern-reservation layer over a semiconductor substrate. The semiconductor substrate has a major surface. A first self-aligned...
2017/0229347 METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE CONTAINING HIGH MOBILITY SEMICONDUCTOR CHANNEL MATERIALS
A method of forming a semiconductor structure is provided. The method includes providing a substrate comprising, from bottom to top, a handle substrate, an...
2017/0229346 Semiconductor Devices, Methods of Manufacture Thereof, and Methods of Singulating Semiconductor Devices
Semiconductor devices, methods of manufacture thereof, and methods of singulating semiconductor devices are disclosed. In some embodiments, a method of...
2017/0229345 METHOD OF FABRICATING DUAL DAMASCENE STRUCTURE
A substrate having thereon a first dielectric layer, a second dielectric layer, and a hard mask layer is provided. A partial via is formed in the second...
2017/0229344 COLUMNAR INTERCONNECTS AND METHOD OF MAKING THEM
Disclosed herein is an interconnect structure, including: a dielectric material layer having a cavity having a height, width and length within a dielectric...
2017/0229343 SEMICONDUCTOR STRUCTURE WITH RESIST PROTECTIVE OXIDE ON ISOLATION STRUCTURE AND METHOD OF MANUFACTURING THE SAME
A method of forming a semiconductor structure includes; (i) forming an isolation structure in a semiconductor substrate, the isolation structure electrically...
2017/0229342 TRANSISTOR FABRICATION TECHNIQUE INCLUDING SACRIFICIAL PROTECTIVE LAYER FOR SOURCE/DRAIN AT CONTACT LOCATION
Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The...
2017/0229341 Method of Forming Trenches
A method of forming a semiconductor device fabrication is described that includes forming a material layer over a substrate, forming a first trench in the...
2017/0229340 METHOD OF FORMING SHALLOW TRENCH ISOLATION (STI) STRUCTURES
A method of forming a trench isolation (e.g., an STI) for an integrated circuit includes forming a pad oxide layer and then a nitride layer over a...
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