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Patent # Description
2017/0243884 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
According to the embodiment, a semiconductor device includes: a stacked body; a columnar portion, an insulating portion; and wall portion. The stacked body...
2017/0243883 SEMICONDUCTOR MEMORY DEVICE
According to an embodiment, a semiconductor memory device comprises a substrate, a plurality of first conductive layers, a memory columnar body, a first...
2017/0243882 METHOD OF VERIFYING LAYOUT OF VERTICAL MEMORY DEVICE
A method of verifying a layout of a vertical memory device includes classifying a plurality of channel holes included in the layout of the vertical memory...
2017/0243881 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
Disclosed is a method of manufacturing a semiconductor device, including: forming a stacked structure including first material layers and second material...
2017/0243880 SEMICONDUCTOR MANUFACTURING DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
According to one embodiment, when a wafer is placed on a base stand and a first frequency voltage is applied to the base stand, the potential of the wafer is...
2017/0243879 THREE DIMENSIONAL MEMORY DEVICE CONTAINING DISCRETE SILICON NITRIDE CHARGE STORAGE REGIONS
Discrete silicon nitride portions can be formed at each level of electrically conductive layers in an alternating stack of insulating layers and the...
2017/0243878 NON-VOLATILE MEMORY DEVICES WITH VERTICALLY INTEGRATED CAPACITOR ELECTRODES
Provided is a vertical non-volatile memory device in which a capacitor constituting a peripheral circuit region is formed as a vertical type so that an area...
2017/0243877 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a substrate having a memory region and a peripheral region that are adjacent to each other, and a plurality of...
2017/0243876 SEMICONDUCTOR DEVICES WITH GRADED DOPANT REGIONS
Most semiconductor devices manufactured today, have uniform dopant concentration, either in the lateral or vertical device active (and isolation) regions. By...
2017/0243875 DOPED GRAPHENE ELECTRODES AS INTERCONNECTS FOR FERROELECTRIC CAPACITORS
A ferroelectric capacitor having a doped graphene bottom electrode and uses thereof are described. The doped graphene bottom electrode layer is deposited on a...
2017/0243874 SEMICONDUCTOR DEVICE
[Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device...
2017/0243873 SEMICONDUCTOR MEMORY DEVICE
According to an embodiment, a semiconductor memory device comprises: a stacked body including control gate electrodes stacked upwardly of a substrate; a...
2017/0243872 SRAM Circuits with Aligned Gate Electrodes
A device includes a Static Random Access Memory (SRAM) array, and an SRAM cell edge region abutting the SRAM array. The SRAM array and the SRAM cell edge...
2017/0243871 PATTERN FORMING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING THE SAME
A method for forming patterns includes forming an etch target layer; etching the etch target layer to form a pre-pattern having a line forming portion and a...
2017/0243870 SEMICONDUCTOR DEVICE WITH FIN TRANSISTORS AND MANUFACTURING METHOD OF SUCH SEMICONDUCTOR DEVICE
A semiconductor device including: a first conductivity type transistor and a second conductivity type transistor, wherein each of the first conductivity type...
2017/0243869 SEMICONDUCTOR DEVICE HAVING A FILLING CONDUCTOR COMPRISING A PLUG PORTION AND A CAP PORTION AND MANUFACTURING...
A semiconductor device includes a semiconductor substrate and at least one gate stack. The gate stack is present on the semiconductor substrate, and the gate...
2017/0243868 Structure and Method for Semiconductor Device
A semiconductor device and methods of forming the same are disclosed. The semiconductor device comprises a substrate; an isolation structure over the...
2017/0243867 PATTERNED GATE DIELECTRICS FOR III-V-BASED CMOS CIRCUITS
Semiconductor devices and methods of making the same include forming a first channel region on a first semiconductor region. A second channel region is formed...
2017/0243866 CMOS CIRCUITS USING N-CHANNEL AND P-CHANNEL GALLIUM NITRIDE TRANSISTORS
CMOS circuits may formed using p-channel gallium nitride transistors and n-channel gallium nitride transistors, wherein both the p-channel gallium nitride...
2017/0243865 SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a first a first transistor configured to operate at a first threshold voltage level. The first transistor includes a first gate...
2017/0243864 ELECTROSTATIC DISCHARGE PROTECTION DEVICE
An electrostatic discharge (ESD) protection device is disclosed including at least an NPN transistor and a PNP transistor coupled between a first node and a...
2017/0243863 PROTECTIVE CIRCUIT AND METHOD FOR PROTECTING A CIRCUIT
A protective circuit (10) comprises a terminal (11), a reference potential terminal (12) and a protective structure (13) that is arranged between the terminal...
2017/0243862 APPARATUS AND METHODS FOR ROBUST OVERSTRESS PROTECTION IN COMPOUND SEMICONDUCTOR CIRCUIT APPLICATIONS
Apparatus and methods for compound semiconductor protection clamps are provided herein. In certain configurations, a compound semiconductor protection clamp...
2017/0243861 LAYOUT PATTERN FOR SRAM AND MANUFACTURING METHODS THEREOF
A layout pattern of a static random access memory, including a first inverter and a second inverter constituting a latch circuit. A first inner access...
2017/0243860 DISPLAY APPARATUS INCLUDING A MICRO LIGHT-EMITTING DIODE
A display apparatus includes a semiconductor substrate, a transistor, and a light-emitting diode. The transistor is disposed on the semiconductor substrate and...
2017/0243859 LIGHT EMITTING DEVICE
A light emitting device includes: a ceramic substrate; a plurality of LED chips; a printed resistor(s) connected in parallel with the plurality of LED chips; a...
2017/0243858 SEMICONDUCTOR PACKAGE INCORPORATING REDISTRIBUTION LAYER INTERPOSER
A semiconductor package is provided. The semiconductor package includes a carrier substrate having opposite first surface and second surface, and a chip stack...
2017/0243857 SEMICONDUCTOR PACKAGE HAVING A HIGH RELIABILITY
A semiconductor package includes a package substrate, a plurality of semiconductor devices stacked on the package substrate, a plurality of underfill fillets...
2017/0243856 SEMICONDUCTOR PACKAGES
A semiconductor package includes a plurality of semiconductor chips on a substrate. The semiconductor chips include a first semiconductor chip, a second...
2017/0243855 SEMICONDUCTOR PACKAGE
A semiconductor package including a mounting board, a first semiconductor chip on the mounting board, the first semiconductor chip having a first peripheral...
2017/0243854 CIRCUIT SUBSTRATE AND METHOD OF MANUFACTURING SAME
A circuit substrate of one aspect of the present invention includes a first substrate body made of a flexible wiring substrate and having a first edge and a...
2017/0243853 ALIGNMENT SYSTEMS AND WAFER BONDING SYSTEMS AND METHODS
Alignment systems, and wafer bonding alignment systems and methods are disclosed. In some embodiments, an alignment system for a wafer bonding system includes...
2017/0243852 ENHANCED CLEANING FOR WATER-SOLUBLE FLUX SOLDERING
An approach to provide an electronic assembly process that includes receiving at least one electronic assembly after a solder reflow process using a...
2017/0243851 APPARATUS FOR ESPECIALLY THERMALLY JOINING MICRO-ELECTROMECHANICAL PARTS
The invention relates to an apparatus for especially thermally joining micro-electromechanical parts (2, 3) in a process chamber (8), comprising a bottom...
2017/0243850 Electronic Arrangement
An electronic arrangement comprising: a carrier; at least one connecting area on the carrier; at least one electronic component, which is fixed at least on the...
2017/0243849 CONDUCTIVE COMPOSITION AND ELECTRONIC PARTS USING THE SAME
A conductive composition, which can form bonded portions and is capable of maintaining a thickness of the bonded portions and bonding strength, and which...
2017/0243848 SOLDER BUMPS FORMED ON WAFERS USING PREFORMED SOLDER BALLS WITH DIFFERENT COMPOSITIONS AND SIZES
Solder-bumped semiconductor substrates (e.g., semiconductor wafers) and methods for forming solder bumped semiconductor substrates are provided, in which...
2017/0243847 SEMICONDUCTOR DEVICE
To provide a technique capable of reducing the chip size of a semiconductor chip and particularly, a technique capable of reducing the chip size of a...
2017/0243846 Connector Structure and Method of Forming Same
Connector structures and methods of forming the same are provided. A method includes forming a first patterned passivation layer on a workpiece, the first...
2017/0243845 FAN-OUT WAFER-LEVEL PACKAGES WITH IMPROVED TOPOLOGY
A fan-out wafer-level-process integrated circuit is provided in which a plurality of interconnects couple to pads on an encapsulated die. The interconnects...
2017/0243844 Semiconductor Device
Disclosed is a semiconductor device suppressed in decrease of reliability. The semiconductor device comprises an electrode pad portion (2) formed on the upper...
2017/0243843 BUMP STRUCTURE, DISPLAY DEVICE INCLUDING A BUMP STRUCTURE, AND METHOD OF MANUFACTURING A BUMP STRUCTURE
A bump structure includes a first bump disposed on a substrate, the first bump including a first metal, at least one antioxidant member surrounded by the first...
2017/0243842 SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF
A semiconductor arrangement and method of formation are provided. The semiconductor arrangement includes a metal trace under at least a first dielectric layer...
2017/0243841 METHOD OF MANUFACTURING PRINTED CIRCUIT BOARD
The present invention comprises a step of forming bump pads on the surface of the substrate, covering the whole surface with a second insulating layer, forming...
2017/0243839 SYSTEMS AND METHODS FOR ACHIEVING UNIFORMITY ACROSS A REDISTRIBUTION LAYER
Systems and methods for achieving uniformity across a redistribution layer are described. One of the methods includes patterning a photoresist layer over a...
2017/0243838 ELECTRONIC DEVICE WITH MIRCOFILM ANTENNA AND RELATED METHODS
An electronic device may include a first substrate, an electrically conductive feed line on the first substrate, an insulating layer on the first substrate and...
2017/0243837 DURABLE, HEAT-RESISTANT MULTI-LAYER COATINGS AND COATED ARTICLES
An article having a surface treated to provide a protective coating structure in accordance with the following method: vapor depositing a first layer on a...
2017/0243836 INTEGRATED CIRCUIT WITH BACKSIDE STRUCTURES TO REDUCE SUBSTRATE WARP
Wafer bowing induced by deep trench capacitors is ameliorated by structures formed on the reverse side of the wafer. The structures on the reverse side include...
2017/0243835 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
In one embodiment, a semiconductor device includes a substrate, and interconnects provided above the substrate. The device further includes a first insulator...
2017/0243834 ELECTRONIC PACKAGE, SEMICONDUCTOR SUBSTRATE OF THE ELECTRONIC PACKAGE, AND METHOD FOR MANUFACTURING THE...
A semiconductor substrate is provided, including a substrate body, a plurality of conductive through holes penetrating the substrate body, and at least one...
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