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Patent # Description
2017/0243833 PACKAGE MODULE AND METHOD OF MANUFACTURING THE SAME
A package module includes first and second components, a conductive wall, and a molding portion. The first component and the second component are disposed on a...
2017/0243832 ELECTRONIC DEVICE MODULE AND METHOD OF MANUFACTURING THE SAME
An electronic device module, includes a substrate including a grounding electrode disposed on a surface of the substrate, an insulating portion encapsulating a...
2017/0243831 VISUAL IDENTIFICATION OF SEMICONDUCTOR DIES
Systems and methods for visual identification of semiconductor dies are described. In some embodiments, a method may include: receiving a semiconductor wafer...
2017/0243830 SEMICONDUCTOR DEVICE INTERCONNECT STRUCTURES FORMED BY METAL REFLOW PROCESS
Methods are devices are provided in which interconnection structures are formed using metal reflow techniques. For example, a method to fabricate a...
2017/0243829 SEMICONDUCTOR STRUCTURE HAVING TAPERED DAMASCENE APERTURE AND METHOD OF THE SAME
A semiconductor structure having tapered damascene aperture is disclosed. The semiconductor structure including an etching stop layer over an inter-layer...
2017/0243828 Semiconductor Device and Method for Producing a Semiconductor Device
A semiconductor device includes a semiconductor body with a front face and a back face, having an active zone located at the front face, a front surface...
2017/0243827 INTERCONNECT STRUCTURE AND METHOD OF FORMING
Aspects of the present disclosure include a method of forming a semiconductor interconnect structure and the interconnect structure. The method includes...
2017/0243826 FAN-OUT PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
A semiconductor package structure including a first semiconductor package is provided. The first semiconductor package includes a first redistribution layer...
2017/0243825 LOW RESISTANCE CONTACT STRUCTURES FOR TRENCH STRUCTURES
An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel...
2017/0243824 LOW RESISTANCE CONTACT STRUCTURES FOR TRENCH STRUCTURES
An electrical device including at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel...
2017/0243823 METHOD, APPARATUS, AND SYSTEM FOR MOL INTERCONNECTS WITHOUT TITANIUM LINER
Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate;...
2017/0243822 BEOL VERTICAL FUSE FORMED OVER AIR GAP
A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the...
2017/0243821 BEOL VERTICAL FUSE FORMED OVER AIR GAP
A method of forming an electrical device that includes forming a first level including an array of metal lines, wherein an air gap is positioned between the...
2017/0243820 Inductor System and Method
A system and method for providing and manufacturing an inductor is provided. In an embodiment similar masks are reutilized to form differently sized inductors....
2017/0243819 STACKED DEVICE, MANUFACTURING METHOD, AND ELECTRONIC INSTRUMENT
The present disclosure relates to a stacked device, a manufacturing method, and an electronic instrument, capable of suppressing adverse effects of noise...
2017/0243818 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a first to a third wiring-line. The first wiring-line is provided on a first layer in a first direction. The second wiring-line...
2017/0243817 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a plurality of first electrode layers stacked; a second electrode layer provided on the first electrode layers; a third...
2017/0243816 INTEGRATED CIRCUIT CHIP PACKAGING
A method of mounting an integrated circuit chip to a circuit board includes placing the integrated circuit chip into a cavity extending from a surface of the...
2017/0243815 REDISTRIBUTION LAYER LINES
Embodiments herein may relate to a package with a dielectric layer having a first face and a second face opposite the first face. A conductive line of a...
2017/0243814 SEMICONDUCTOR PACKAGE
A semiconductor package includes a substrate and a flip-chip on the substrate The flip-chip includes first bump pads and second bump pads on an active surface...
2017/0243813 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a first...
2017/0243812 SEMICONDUCTOR DEVICE
A semiconductor device includes a substrate, a semiconductor element, a terminal and a solder outflow prevention part. The semiconductor element is fixed on...
2017/0243811 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device includes preparing a semiconductor chip having a back surface made of a Cu layer. The semiconductor chip is...
2017/0243810 ELECTRONIC DEVICE AND METHODS OF PROVIDING AND USING ELECTRONIC DEVICE
Some embodiments include a method of providing an electronic device. The method can comprise: providing a first device substrate; providing one or more first...
2017/0243809 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device according to an embodiment includes a semiconductor layer having a first plane and a second plane, an insulating layer provided in the...
2017/0243808 JOINED BODY AND MANUFACTURING METHOD THEREOF, AND COOLING DEVICE AND ELECTRONIC EQUIPMENT USING COOLING DEVICE
A joined body of the embodiments is a joined body which includes copper and resin, wherein in a joint surface of the copper to the resin, a triazine thiol...
2017/0243807 PACKAGING FOR HIGH POWER INTEGRATED CIRCUITS AND INFRARED EMITTER ARRAYS
A product and method for packaging high power integrated circuits or infrared emitter arrays for operation through a wide range of temperatures, including...
2017/0243806 Powermap Optimized Thermally Aware 3D Chip Package
A semiconductor package includes a substrate, an integrated circuit disposed on the substrate, a memory support disposed on the integrated circuit, stacked...
2017/0243805 ARRANGEMENT FOR SUBSEA COOLING OF SEMICONDUCTOR MODULES
An arrangement for subsea cooling of a semiconductor module. The arrangement includes a tank. The tank is filled with a dielectric fluid. The arrangement...
2017/0243804 RESIN STRUCTURE, AND ELECTRONIC COMPONENT AND ELECTRONIC DEVICE USING THE STRUCTURE
Provided herein is a resin structure having high heat dissipation, and desirable adhesion at the interface with a heat generating device. The resin structure...
2017/0243803 THERMALLY ENHANCED SEMICONDUCTOR ASSEMBLY WITH THREE DIMENSIONAL INTEGRATION AND METHOD OF MAKING THE SAME
A thermally enhanced semiconductor assembly with three dimensional integration includes a semiconductor chip electrically coupled to a wiring board by bonding...
2017/0243802 INTEGRATED CIRCUIT CHIP PACKAGING
An electrical circuit device includes a circuit board including a cavity extending from a top surface of the circuit board to an embedded conductor, an...
2017/0243801 ELECTRONIC COMPONENT MOUNTING STRUCTURE
An electronic component mounting structure includes a terminal of an electronic component package and a chip heat radiating member. The terminal is soldered on...
2017/0243800 Interconnect Structures for Wafer Level Package and Methods of Forming Same
A device package is provided. The device package includes a first die and a second die. A top surface of the first die is offset from a top surface of the...
2017/0243799 SUBSTRATE FOR INTEGRATED CIRCUIT PACKAGE
The present invention relates to a substrate for an integrated circuit package and, more specifically, to a substrate for an integrated circuit package, which...
2017/0243798 FINGERPRINT SENSOR AND MANUFACTURING METHOD THEREOF
A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various...
2017/0243797 DISPLAY DRIVING DEVICE
Disclosed is a display driving device including a bonding resistance measurement circuit. The display driving device may include: first and second pads bonded...
2017/0243796 APPARATUS AND METHOD FOR CUTTING A WAFER THAT IS SUBSTANTIALLY COVERED BY AN OPAQUE MATERIAL
A wafer cutting apparatus comprises a wafer positioning device for holding a wafer that is substantially covered with an opaque material such as molding...
2017/0243795 INTEGRATED CIRCUIT SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
A method of manufacturing a wafer. The method includes providing a wafer and testing the wafer. Based on a test result, a substance is selectively provided on...
2017/0243794 METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT SUBSTRATE
A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one...
2017/0243793 System and Method for a Microfabricated Fracture Test Structure
According to an embodiment, a micro-fabricated test structure includes a structure mechanically coupled between two rigid anchors and disposed above a...
2017/0243792 METHOD TO IMPROVE HCI PERFORMANCE FOR FINFET
A semiconductor device includes a substrate structure, multiple fins protruding from the substrate structure, each of the fins having a first portion, a second...
2017/0243791 METHODS OF FORMING GRAPHENE CONTACTS ON SOURCE/DRAIN REGIONS OF FINFET DEVICES
One illustrative method disclosed herein includes forming a gate structure above a portion of a fin and performing a first epitaxial growth process to form a...
2017/0243790 METHODS OF PERFORMING CONCURRENT FIN AND GATE CUT ETCH PROCESSES FOR FINFET SEMICONDUCTOR DEVICES AND THE...
A method includes forming a plurality of fins above a substrate. A plurality of gate structures is formed above the plurality of fins. A first mask layer is...
2017/0243789 DISTINCT GATE STACKS FOR III-V-BASED CMOS CIRCUITS COMPRISING A CHANNEL CAP
Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed...
2017/0243788 LAYOUT STRUCTURE FOR SEMICONDUCTOR INTEGRATED CIRCUIT
Disclosed herein is a technique for providing a layout structure for a semiconductor integrated circuit with SOI transistors with an antenna error that could...
2017/0243787 WORKPIECE PROCESSING METHOD
A processing method of processing a workpiece on which a plurality of intersecting planned dividing lines are set is provided. The processing method includes a...
2017/0243786 WAFER PROCESSING METHOD
Disclosed herein is a wafer processing method for dividing a wafer into individual device chips along division lines. The wafer processing method includes a...
2017/0243785 INTEGRATED CIRCUIT SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME
A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one...
2017/0243784 METAL LAYER TIP TO TIP SHORT
Techniques relate to forming an integrated circuit. Trench contacts are formed on top of at least one source and drain of an intermediate structure. An...
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