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Patent # Description
2017/0263338 Exothermic Transmutation Method
An exothermic transmutation method for at least partially deactivating radioactive material, the method comprising the steps of: --Arranging a dusty compound...
2017/0263337 METHODS AND APPARATUS FOR ENHANCED NUCLEAR REACTIONS
Nuclear fusion processes with enhanced rates may be realized by providing energetic electrons in an environment containing a suitable fuel gas, a liquid fuel...
2017/0263336 MEMORY AND MEMORY DEVICE
According to one embodiment, a memory includes a magnetoresistive element, a reference cell, a sense amplifier comparing a first current flowing in the...
2017/0263335 SEMICONDUCTOR TEST SYSTEM DURING BURN-IN PROCESS
A command generation circuit, test control circuit, semiconductor device, semiconductor system, and or a test method may be provided. The semiconductor device...
2017/0263334 SEMICONDUCTOR STORAGE DEVICE AND TEST METHOD THEREOF USING A COMMON BIT LINE
Provided is a semiconductor storage device including: first memory cells; first word lines; first bit lines; a first common bit line; second memory cells;...
2017/0263333 MULTI-PORT MEMORY, SEMICONDUCTOR DEVICE, AND MEMORY MACRO-CELL
A multi-port memory includes a memory cell, first and second word lines, first and second bit lines, first and second address terminals, and an address control...
2017/0263332 STREAMING STRESS TESTING OF CACHE MEMORY
An aspect includes a method of streaming stress testing in a cache memory system. The method includes configuring, by a streaming stress generator, one or more...
2017/0263331 MEMORY SYSTEM
According to one embodiment, a memory system includes a non-volatile memory, a memory interface that performs programming and reading out with respect to the...
2017/0263330 GATE DRIVE CIRCUIT AND SHIFT REGISTER CIRCUIT
The present disclosure provides a gate drive circuit including a plurality of cascaded shift register circuits, each shift register circuit include a signal...
2017/0263329 MAGNETIC MEMORY DEVICE
According to the embodiment, a magnetic memory device includes a magnetic body. The magnetic body includes first and second extending regions, and a first...
2017/0263328 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
To provide a semiconductor device equipped with anti-fuse memory cells, which is capable of improving read-out accuracy of information. There is provided a...
2017/0263327 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
The present technique relates to an electronic device, and more particularly, to a semiconductor memory device and an operating method thereof. A semiconductor...
2017/0263326 SEMICONDUCTOR MEMORY DEVICE
A memory device capable of narrowing the threshold voltage distribution thereof includes word lines, bit lines, memory cells, a word line driver configured to...
2017/0263325 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes a first transistor which includes a first end coupled to a first node, a second end, and a...
2017/0263324 SECTOR RETIREMENT FOR SPLIT-GATE MEMORY
A memory is provided. The memory includes an array of non-volatile memory (NVM) cells arranged in a plurality sectors. A control gate driver circuit has an...
2017/0263323 Circuit and Method for Reading a Memory Cell of a Non-Volatile Memory Device
A circuit for reading a memory cell of a non-volatile memory device provided with a memory array with cells arranged in wordlines and bitlines, among which a...
2017/0263322 MEMORY DEVICE
A memory device includes a memory cell array including a plurality of memory cell groups, and a decoder circuit configured to control selection of the memory...
2017/0263321 NONVOLATILE MEMORY DEVICE AND DATA STORAGE DEVICE INCLUDING THE SAME
A data storage device includes a nonvolatile memory device; and a controller suitable for providing a normal erase command or a fine erase command to the...
2017/0263320 METHOD FOR WRITING INTO AND READING A MULTI-LEVELS EEPROM AND CORRESPONDING MEMORY DEVICE
During a phase of programming the cell, a first voltage is applied to the source region and a second voltage, higher than the first voltage, is applied to the...
2017/0263319 ROW DECODER FOR A NON-VOLATILE MEMORY DEVICE, AND NON-VOLATILE MEMORY DEVICE
A non-volatile memory device includes a memory array having memory cells arranged in wordlines and receiving a supply voltage. A row decoder includes an input...
2017/0263318 SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM
According to one embodiment, a semiconductor memory device includes: a first memory unit including first to fourth memory cells; a second memory unit including...
2017/0263317 ELECTRONIC DEVICE INCLUDING VARIABLE RESISTANCE ELEMENT AND METHOD FOR OPERATING THE SAME
A method for operating an electronic device including a variable resistance element comprises performing a reset operation on the variable resistance element....
2017/0263316 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device comprises a memory cell and a first circuit. The first circuit is configured to generate a write...
2017/0263315 RESISTIVE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME
A semiconductor memory device contains a first memory cell including a first variable resistive element, and a first circuit for controlling a write performed...
2017/0263314 MEMORY CELL LOCATED PULSE GENERATOR
The present disclosure generally relates to a memory cell and methods for generating a pulse within the memory cell. As such, a geometric arrangement of...
2017/0263313 MEMORY DEVICE
A device is disclosed that includes a driver, a sinker and a memory column. The memory column includes a plurality of resistive memory cells each being...
2017/0263312 MEMORY SYSTEM AND METHOD OF CONTROLLING THEREOF
According to one embodiment, a memory system acquires HB information and SB1 information through SB4 information on each of four pages including LOWER, MIDDLE,...
2017/0263311 SYSTEMS AND METHODS FOR ADAPTIVE READ LEVEL ADJUSTMENT
Reading requested data from flash memory using a first read level voltage. A number of first bit-value errors and a number of second bit-value errors is...
2017/0263310 READING MEMORY CELLS
A first read operation is performed using a first voltage level to read data from a memory array. An instant bit count corresponding to a number of bits in the...
2017/0263309 10-Transistor Non-Volatile Static Random-Access Memory Using A Single Non-Volatile Memory Element And Method Of...
A memory including an array of nvRAM cells and method of operating the same are provided. Each nvRAM cell includes a volatile charge storage circuit, and a...
2017/0263308 SRAM MEMORY BIT CELL COMPRISING N-TFET AND P-TFET
SRAM memory bit cell comprising: a n-TFET and a p-TFET; a storage node formed by the connection of a first electrode of the n-TFET to a first electrode of...
2017/0263307 SEMICONDUCTOR STORAGE DEVICE
A semiconductor storage device having a plurality of low power consumption modes is provided. The semiconductor storage device includes a plurality of memory...
2017/0263306 APPARATUSES AND METHODS FOR LOGIC/MEMORY DEVICES
Apparatuses and methods are provided for logic/memory devices. An example apparatus comprises a plurality of memory components adjacent to and coupled to one...
2017/0263305 METHOD OF DETECTING MOST FREQUENTLY ACCESSED ADDRESS OF SEMICONDUCTOR MEMORY BASED ON PROBABILITY INFORMATION
A method of managing a semiconductor memory is provided which includes sampling a row address from an access stream on a memory cell array according to a...
2017/0263304 MEMORY CELL SENSING WITH STORAGE COMPONENT ISOLATION
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ferroelectric memory cell may be selected using a selection...
2017/0263303 PARALLEL ACCESS TECHNIQUES WITHIN MEMORY SECTIONS THROUGH SECTION INDEPENDENCE
A memory device having a plurality sections of memory cells, such as ferroelectric memory cells (hybrid RAM (HRAM) cells) may provide for concurrent access to...
2017/0263302 OFFSET COMPENSATION FOR FERROELECTRIC MEMORY CELL SENSING
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. Offsets in the threshold voltage of switching components (e.g.,...
2017/0263301 DATA READING PROCEDURE BASED ON VOLTAGE VALUES OF POWER SUPPLIED TO MEMORY CELLS
A storage device includes a memory cell array, a voltage detector disposed to detect a voltage of power supplied to the memory cell array, and a controller....
2017/0263300 WRITE VERIFY PROGRAMMING OF A MEMORY DEVICE
A memory device is configured to identify a set of bit cells to be changed from a first state to a second state. In some examples, the memory device may apply...
2017/0263299 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes a memory cell and a first circuit. The memory cell includes a variable resistance element....
2017/0263298 SEMICONDUCTOR STORAGE DEVICE
According to one embodiment, a semiconductor storage device includes a first memory area, a first selection circuit for selecting a bit line of the first...
2017/0263297 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes: a first bit line; a first source line; a first word line; a first control line; a first...
2017/0263296 MAGNETIC MEMORY DEVICE
According to one embodiment, the magnetic memory device includes a first magnetoresistive element and a second magnetoresistive element which are adjacent to...
2017/0263295 MEMORY ACTIVATION METHOD AND APPARATUS, AND MEMORY CONTROLLER
A first memory access request is obtained, where the first memory access request is used to request to access a first sub-row in a memory. A to-be-scheduled...
2017/0263294 SEMICONDUCTOR MEMORY DEVICE CAPABLE OF PERFORMING READ OPERATION AND WRITE OPERATION SIMULTANEOUSLY
A semiconductor memory device includes a charge storage element, a read transistor, and a write transistor. The charge storage element is for preserving a...
2017/0263293 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
In an embodiment, a semiconductor memory device may include a memory cell array, a plurality of page buffers, and a control logic. The memory cell array may...
2017/0263292 APPARATUS FOR POWER MANAGEMENT
Apparatus include an array of memory cells, a controller to perform access operations on the array of memory cells, a clock signal node, a counter having an...
2017/0263291 SEMICONDUCTOR DEVICE
The circuit scale of a semiconductor device that can perform arithmetic processing of analog data is reduced. In the semiconductor device, a memory cell is...
2017/0263290 DISK DRIVE
According to one embodiment, a disk drive includes a base including a bottom wall and a side wall, a cover including a top plate screwed on the side wall, a...
2017/0263289 MARKING STORED VIDEO
A system for marking video comprises an input interface, a processor, and an output interface. The input interface is configured to receive event recorder data...
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