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Patent # Description
2017/0271246 LEADFRAME LEADS HAVING FULLY PLATED END FACES
A semiconductor device includes a leadframe, a semiconductor die attached to the leadframe, and an encapsulation material encapsulating the semiconductor die...
2017/0271245 Direct Selective Adhesion Promotor Plating
A lead frame strip having a plurality of unit lead frames is provided. Each of the unit lead frames have a die paddle and a plurality of leads extending away...
2017/0271244 LEAD FRAME WITH SOLDER SIDEWALLS
A leadframe wherein the outer sidewalls of the leadframe that are exposed by sawing during singulation are comprised of greater than 50% solder. A leadframe...
2017/0271243 MULTILAYER SUBSTRATE, COMPONENT MOUNTED BOARD, AND METHOD FOR PRODUCING COMPONENT MOUNTED BOARD
A multilayer substrate includes a flexible element assembly including a principal surface, a first to an n-th external electrode disposed on the principal...
2017/0271242 Interconnection Structure with Confinement Layer
An interconnection structure and method disclosed for providing an interconnection structure that includes conductive features having reduced topographic...
2017/0271241 Semiconductor Device and Method of Forming Low Profile Fan-Out Package with Vertical Interconnection Units
A semiconductor device includes a semiconductor die. A first interconnect structure is disposed over a peripheral region of the semiconductor die. A...
2017/0271240 POWER SEMICONDUCTOR MODULE AND COOLER
A power semiconductor module includes a laminate substrate; a semiconductor element joined to a front surface of the laminate substrate; a base plate 14 joined...
2017/0271239 SEMICONDUCTOR MODULE AND MANUFACTURING METHOD OF SEMICONDUCTOR MODULE
A semiconductor module is provided, including: a cooling-target device; a first cooling unit on which the cooling-target device is placed and that has a flow...
2017/0271238 BONDED BODY, POWER MODULE SUBSTRATE WITH HEAT SINK, HEAT SINK, METHOD OF MANUFACTURING BONDED BODY, METHOD OF...
The present invention is a bonded body in which an aluminum member constituted by an aluminum alloy, and a metal member constituted by copper, nickel, or...
2017/0271237 BONDED BODY, POWER MODULE SUBSTRATE WITH HEAT SINK, HEAT SINK, METHOD OF MANUFACTURING BONDED BODY, METHOD OF...
The present invention is a bonded body in which an aluminum member constituted by an aluminum alloy, and a metal member constituted by copper, nickel, or...
2017/0271236 SUBSTRATE FOR SEMICONDUCTOR DEVICES
Provided is a substrate for semiconductor devices comprising: an insulating substrate; and a first metal board having a plurality of sides and formed on a...
2017/0271235 COMPOUND SEMICONDUCTOR DEVICE STRUCTURES COMPRISING POLYCRYSTALLINE CVD DIAMOND
A semiconductor device structure includes a layer of single crystal compound semiconductor material; and a layer of polycrystalline CVD diamond material. The...
2017/0271234 BONDING WIRE-TYPE HEAT SINK STRUCTURE FOR SEMICONDUCTOR DEVICES
The present invention discloses a bonding-wire-type heat sink structure for semiconductor devices. An embodiment of the said bonding-wire-type heat sink...
2017/0271233 SEMICONDUCTOR DEVICE
A semiconductor device includes an electronic component connected to a component pad of a wiring substrate, a connection member connected to a connection pad...
2017/0271232 UNDERFILL DISPENSING USING FUNNELS
Arrays of objects on a substrate having void-free underfill as well as methods and systems of forming the same include forming a void-free layer of underfill...
2017/0271231 SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device includes a substrate, semiconductor chips mounted on the substrate, a sealing resin layer that seals the...
2017/0271230 MANUFACTURING METHOD OF MOLDED PRODUCT AND MOLDED PRODUCT
Provided is a molded product manufacturing method, including attachment of attaching a partially exposed member that extends from inside a sealed portion in...
2017/0271229 Spatially selective roughening of encapsulant to promote adhesion with functional structure
An electronic component which comprises an electrically conductive carrier, an electronic chip on the carrier, an encapsulant encapsulating at least part of at...
2017/0271228 CARRIERLESS CHIP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME
Disclosed is a carrierless chip package for integrated circuit devices, and various methods of make same. In one illustrative embodiment, the device includes...
2017/0271227 INTEGRATED FAN-OUT PACKAGE, INTEGRATED FAN-OUT PACKAGE ARRAY, AND METHOD OF MANUFACTURING INTEGRATED FAN-OUT...
An integrated fan-out package including a die, an insulating encapsulation, a filler, and a redistribution circuit structure is provided. The insulating...
2017/0271226 TETRAMETHYLBIPHENOL TYPE EPOXY RESIN, EPOXY RESIN COMPOSITION, CURED PRODUCT, AND SEMICONDUCTOR SEALING MATERIAL
The present invention relates to a tetramethylbiphenol type epoxy resin having a content of a sodium ion of 1 to 12 ppm which is determined by measurement by...
2017/0271225 ELECTRONIC DEVICE
An electronic device includes an electronic element, and a wire bonded to the electronic element. The electronic element includes a bonding pad to which the...
2017/0271224 SEMICONDUCTOR DEVICE
A semiconductor device, including a plurality of semiconductor units disposed in a matrix, and a capsule encapsulating the plurality of semiconductor units....
2017/0271223 System and Method for Bonding Package Lid
Disclosed herein is a device having a shaped seal ring comprising a workpiece, the workpiece comprising at least one dielectric layer disposed on a first side...
2017/0271222 ELECTRONIC ELEMENT PACKAGE AND METHOD FOR MANUFACTURING THE SAME
The present disclosure relates to an electronic element package and a method of manufacturing the same. The electronic element package includes a substrate, an...
2017/0271221 SEMICONDUCTOR PACKAGE
A semiconductor package and die assembly with a package having an exterior surface and an interior space, the interior space defined by a first side wall, and...
2017/0271220 INLINE MONITORING OF TRANSISTOR-TO-TRANSISTOR CRITICAL DIMENSION
In one aspect of the present disclosure, a method is provided, the method including providing a test region in an upper surface region of a semiconductor...
2017/0271219 SCANNING ACOUSTIC MICROSCOPE SENSOR ARRAY FOR CHIP-PACKAGING INTERACTION PACKAGE RELIABILITY MONITORING
A method includes forming a flip-chip module including a chip connected to a substrate with a layer of underfill material adhered to the chip and the...
2017/0271218 CONTROL DEVICE, SUBSTRATE PROCESSING SYSTEM, SUBSTRATE PROCESSING METHOD, AND PROGRAM
Provided is a control device for controlling an operation of a substrate processing apparatus that performs a predetermined processing on a substrate. The...
2017/0271217 IN-SITU CALIBRATION STRUCTURES AND METHODS OF USE IN SEMICONDUCTOR PROCESSING
Systems and methods of in-situ calibration of semiconductor material layer deposition and Removal processes are disclosed. Sets of test structures including...
2017/0271216 METHOD OF MANUFACTURING AN INTEGRATED CIRCUIT SUBSTRATE
A method of manufacturing a wafer. The method includes providing a wafer that includes a plurality of semiconductor device structures, and testing at least one...
2017/0271214 PATTERN ACCURACY DETECTING APPARATUS AND PROCESSING SYSTEM
A pattern accuracy detecting apparatus includes a stage for supporting a substrate, an optical warpage detecting unit that measures a shape of a substrate...
2017/0271213 METHODS OF PREDICTING UNITY GAIN FREQUENCY WITH DIRECT CURRENT AND/OR LOW FREQUENCY PARAMETERS
Various embodiments include approaches for predicting unity gain frequency in a MOSFET. In some cases, a method includes predicting a unity gain frequency...
2017/0271212 SOLID SOURCE DOPING FOR SOURCE AND DRAIN EXTENSION DOPING
A method is provided for solid source doping for source and drain extensions. According to one embodiment, the method includes providing a substrate containing...
2017/0271211 HYBRID INTEGRATION FABRICATION OF NANOWIRE GATE-ALL-AROUND GE PFET AND POLYGONAL III-V PFET CMOS DEVICE
The present invention provides a method of manufacturing nanowire semiconductor device. In the active region of the PMOS the first nanowire is formed with high...
2017/0271210 SUBSTRATE DIVIDING METHOD
A substrate dividing method which can thin and divide a substrate while preventing chipping and cracking from occurring. This substrate dividing method...
2017/0271209 Methods of Packaging Semiconductor Devices and Structures Thereof
Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes...
2017/0271208 WAFER PROCESSING METHOD
A wafer processing method for divides a wafer into individual device chips along a plurality of division lines. The method includes forming a dividing groove...
2017/0271207 Novel 3D Integration Method Using SOI Substrates And Structures Produced Thereby
A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon...
2017/0271206 METHOD FOR FORMING SEMICONDUCTOR STRUCTURE
A semiconductor structure and a method for forming the semiconductor structure are provided. In various embodiments, the method for forming a semiconductor...
2017/0271205 Semiconductor Device and Method
A method of forming a semiconductor device is provided. Metallic interconnects are formed in a dielectric layer of the semiconductor device. A hard mask is...
2017/0271204 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE
A method for manufacturing a semiconductor device includes generating a layout including a first conductive pattern region and a second conductive pattern...
2017/0271203 Semiconductor Device and Method
A method of manufacturing a semiconductor device includes the step of positioning a patterned mask over a dielectric layer. The dielectric layer comprises a...
2017/0271202 FORMING SELF-ALIGNED VERTICAL INTERCONNECT ACCESSES (VIAs) IN INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS (ICs)
Forming self-aligned vertical interconnect accesses (vias) in interconnect structures for integrated circuits (ICs) is disclosed. To reduce or avoid...
2017/0271201 METHOD OF MANUFACTURING A GERMANIUM-ON-INSULATOR SUBSTRATE
A method of manufacturing a germanium-on-insulator substrate is disclosed. The method comprises: providing (102) a first semiconductor substrate, and a second...
2017/0271200 SILICON-ON-PLASTIC SEMICONDUCTOR DEVICE WITH INTERFACIAL ADHESION LAYER
A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a polymer substrate and an interfacial layer...
2017/0271199 SEMICONDUCTOR DEVICE WITH LOCALIZED CARRIER LIFETIME REDUCTION AND FABRICATION METHOD THEREOF
A method of fabricating a semiconductor structure includes forming an isolation feature in a substrate, removing a portion of the isolation feature and a...
2017/0271198 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate. A first set of recesses is formed in the first...
2017/0271197 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region, a second region, and a third region; forming...
2017/0271196 Methods For Gapfill In High Aspect Ratio Structures
Methods for seam-less gapfill comprising sequentially depositing a film with a seam, reducing the height of the film to remove the seam and repeating until a...
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