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Patent # Description
2017/0271043 CONDUCTIVE FILM, AND TOUCH PANEL, DISPLAY, TOUCH SENSOR, AND SOLAR CELL USING THE SAME
A conductive film includes a film substrate and a conductive layer formed on at least one surface of the film substrate. The film substrate and the conductive...
2017/0271042 INSULATION MATERIAL
[Problem] To provide an insulation material that has an excellent volume resistivity while retaining the balance among various capabilities including the...
2017/0271041 COMPOSITION FOR FORMING COAT-TYPE INSULATING FILM
Provided is an insulating coating composition. The composition is highly safe, in which an organic material to form an insulating film is dissolved highly...
2017/0271040 POLYMER COMPOSITES WITH ELECTROMAGNETIC INTERFERENCE MITIGATION PROPERTIES
Polymer composites that are suitable for use as electromagnetic interference mitigaters include a lossy polymeric matrix, ceramic particles dispersed within...
2017/0271039 HIGH-ASPECT RATIO STRUCTURE PRODUCTION METHOD, ULTRASONIC PROBE PRODUCTION METHOD USING SAME, AND HIGH-ASPECT...
A high-aspect ratio structure production method and an ultrasonic probe production method of the present invention include: forming, in a principal surface of...
2017/0271038 METHOD OF MANUFACTURING A RADIATION SOURCE
An equatorial anthropic radiation source and a method of making an equatorial anthropic radiation source are described. The radiation source is useful in...
2017/0271037 High Output Accelerator Neutron
An accelerator neutron source (ANS) including a field ionization (FI) array configured to generate deuterium and tritium ions and a plasma for containing the...
2017/0271036 PROCESSES, SYSTEMS, AND APPARATUS FOR CYCLOTRON PRODUCTION OF TECHNETIUM-99M
A system for producing technetium-99m from molybdate-100. The system comprises: a target capsule apparatus for housing a Mo-100-coated target plate; a target...
2017/0271035 GARMENT WITH ELECTROMAGNETIC RADIATION SHIELDED POCKET
A garment that shields a wearer from electromagnetic radiation may generally have a length of fabric forming the garment. The wearable garment may be virtually...
2017/0271034 METHOD OF MAKING A NUCLEAR FUEL PELLET FOR A NUCLEAR POWER REACTOR
A method of making a nuclear fuel pellet for a nuclear power reactor. The method includes providing a nuclear fuel material in powder form, pressing the powder...
2017/0271033 FROTH SEPARATION IN A MOLTEN SALT REACTOR
A molten salt reactor includes a reactor vessel and a molten salt contained within the reactor vessel and undergoing a nuclear reaction. The molten salt...
2017/0271032 METHODS, APPARATUS, AND SYSTEM FOR GLOBAL HEALING OF WRITE-LIMITED DIE THROUGH BIAS TEMPERATURE INSTABILITY
We disclose methods, apparatus, and systems for improving semiconductor device writeability through bias temperature instability. Such a device may comprise a...
2017/0271031 UPDATING READ VOLTAGES
A device includes a memory and a controller coupled to the memory. The controller is configured to associate a first value of a memory access parameter with a...
2017/0271030 METHOD AND SYSTEM FOR USING DOWNGRADED FLASH DIE FOR CACHE APPLICATIONS
A method and apparatus for using low-cost un-qualified dies suitable for an SSD cache application in an SSD cache are disclosed. Embodiments of the present...
2017/0271029 RAID DECODING ARCHITECTURE WITH REDUCED BANDWIDTH
A RAID decoding system for performing a Built in Self-Test (BIST) includes: an Error Insertion block for inserting errors into a first Reed-Solomon (RS)...
2017/0271028 METHOD FOR TESTING PERFORMANCE OF A STORAGE DEVICE AND CORRESPONDING DEVICE
Performance evaluation of a storage device, for example a storage device connected to a Set Top Box, for evaluating its suitability for supporting DVR/PVR...
2017/0271027 METHODS AND SYSTEMS OF TESTING INTERFACES OF COMPUTER STORAGE FOR STORAGE VULNERABILITIES
Embodiments include methods, and computer system, and computer program products for testing directly and indirectly anchored interfaces for vulnerabilities...
2017/0271026 MEMORY AND SYSTEM INCLUDING THE SAME
There may be provided a memory or memory system. A memory may include an active cell array comprising a plurality of unit cells coupled to a word line and...
2017/0271025 SEMICONDUCTOR STORAGE DEVICE
According to one embodiment, a semiconductor storage device includes: a NAND string with a first set of memory cells including a first memory cell; and a...
2017/0271024 DATA STORAGE DEVICE AND OPERATING METHOD THEREOF
A data storage device includes a controller configured to control data to be written in a first page; and a nonvolatile memory device configured to perform a...
2017/0271023 MEMORY DEVICE
A memory device includes memory cells, word lines that are each connected to gates of a plurality of the memory cells, bit lines that are each connected to a...
2017/0271022 DETERMINATION OF A READ VOLTAGE TO BE APPLIED TO A PAGE BASED ON READ VOLTAGES OF OTHER PAGES
A memory system includes a non-volatile memory and a controller. The controller is configured to maintain a relationship between a first parameter value and a...
2017/0271021 MEMORY DEVICE
A memory device includes a semiconductor column extending above a substrate, a first conductive layer on a first side of the semiconductor column, a second...
2017/0271019 NON-VOLATILE MEMORY DEVICE AND METHOD FOR OPERATING NON-VOLATILE MEMORY DEVICE
A non-volatile memory device includes: a plurality of cache latches; a pair of input/output lines; a plurality of switches, each couples a corresponding cache...
2017/0271018 SEMICONDUCTOR DEVICE, PRE-WRITE PROGRAM, AND RESTORATION PROGRAM
When a control circuit has received a first erase command, the control circuit controls performing a first pre-write process to allow a first storage device...
2017/0271017 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device according to an embodiment includes: a memory cell array including a plurality of memory cells that are NAND-connected; and a...
2017/0271016 NONVOLATILE MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME
In a method of programming a three-dimensional nonvolatile memory device, a program loop is executed at least one time. The program loop includes a programming...
2017/0271015 STORAGE DEVICE AND METHOD OF CONTROLLING THE STORAGE DEVICE
A storage device includes bit lines including a first bit line and a second bit line, memory units including a first memory string having memory cells...
2017/0271014 MEMORY CELL PROGRAMMING UTILIZINGCONDITIONAL ENABLING OF MEMORY CELLS
Methods of operating a memory include determining indications of programming voltages sufficient to program respective groups of memory cells of a plurality of...
2017/0271013 3D FLASH MEMORY DEVICE HAVING DIFFERENT DUMMY WORD LINES AND DATA STORAGE DEVICES INCLUDING SAME
A three-dimensional (3D) flash memory includes a first dummy word line disposed between a ground select line and a lowermost main word line, and a second dummy...
2017/0271012 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
Provided herein are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include a memory cell array, peripheral...
2017/0271011 A CONTENT ADDRESSABLE MEMORY, AN INDEX GENERATOR, AND A REGISTERED INFORMATION UPDATE METHOD
A content addressable memory according to the present invention includes plural index generators, an output unit, and a controller. The plural index generators...
2017/0271010 FERAM-DRAM HYBRID MEMORY
Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. One method includes determining whether to access a first...
2017/0271009 SELECTOR RELAXATION TIME REDUCTION
In one example, a volatile selector is switched from a low conduction state to a first high conduction state with a first voltage level and then the first...
2017/0271008 SEMICONDUCTOR MEMORY DEVICE
According to one embodiment, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory...
2017/0271007 SEMICONDUCTOR MEMORY DEVICE
According to embodiments, a semiconductor memory device includes a first electrode, a second electrode, a memory cell, and a control circuit. The memory cell...
2017/0271006 MEMORY CELLS HAVING A PLURALITY OF RESISTANCE VARIABLE MATERIALS
Resistance variable memory cells having a plurality of resistance variable materials and methods of operating and forming the same are described herein. As an...
2017/0271005 READING CIRCUIT FOR RESISTIVE MEMORY
A circuit for reading a programmed resistive state of resistive elements of a resistive memory, wherein each resistive element may be programmed to be in a...
2017/0271004 DETERMINING A STATE OF MEMRISTORS IN A CROSSBAR ARRAY
In one example in accordance with the present disclosure a method of determining a state of a memristor in a crossbar array is described. In the method a bias...
2017/0271003 DETERMINING RESISTANCE STATES OF MEMRISTORS IN A CROSSBAR ARRAY
In one example in accordance with the present disclosure a method of determining a resistance state of a memristor in a crossbar array is disclosed. In the...
2017/0271002 RESISTANCE CHANGE MEMORY DEVICE CONFIGURED FOR STATE EVALUATION BASED ON REFERENCE CELLS
The disclosed technology generally relates to memory devices and more particularly to memory devices based on resistance change, and to systems and methods for...
2017/0271001 DETERMINING A CURRENT IN A MEMORY ELEMENT OF A CROSSBAR ARRAY
A method of determining a current in a memory element of a crossbar array is described. In the method, a number of pre-access operations are initiated. Each...
2017/0271000 SEMICONDUCTOR MEMORY DEVICE AND CONTROLLING METHOD THEREOF
The control unit performs a first writing operation to obtain a first threshold voltage distribution, and a second writing operation to obtain a second...
2017/0270999 STATIC RANDOM ACCESS MEMORY (SRAM) WRITE ASSIST CIRCUIT WITH IMPROVED BOOST
Approaches for a write assist circuit are provided. The write assist circuit includes a boost capacitor with a first node coupled to a bitline through control...
2017/0270998 REDUCED SWING BIT-LINE APPARATUS AND METHOD
Described is an apparatus which comprises: a bit-line (BL) read port; a first local bit-line (LBL) coupled to the BL read port; a second LBL; and one or more...
2017/0270997 SEMICONDUCTOR DEVICES RELATING TO A REFRESHING OPERATION
A semiconductor device may be provided. The semiconductor device may include an address input circuit and a target address generation circuit. The address...
2017/0270996 SEMICONDUCTOR MEMORY DEIVCE AND ACCESSING METHOD THEREOF
The semiconductor memory device selectively switches at least two banks based on an input parallel address for writing or reading data, and includes a control...
2017/0270995 CIRCUITS AND METHODS FOR DQS AUTOGATING
In one aspect, a method includes receiving a differential strobe signal including first and second components; buffering, by a first buffer, both the first and...
2017/0270994 SIMULTANEOUS WRITE AND READ CALIBRATION OF AN INTERFACE WITHIN A CIRCUIT
To calibrate an electronic circuit, a calibration controller tests the electronic circuit with an initial separate read check allowing for a read delay and...
2017/0270993 SEMICONDUCTOR DEVICE
To provide a memory cell for storing multilevel data that is less likely to be affected by variations in characteristics of transistors and that is capable of...
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