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Patent # Description
2017/0278988 SCREEN PRINTING ELECTRICAL CONTACTS TO NANOSTRUCTURED AREAS
A process is provided for contacting a nanostructured surface. The process may include (a) providing a substrate having a nanostructured material on a surface,...
2017/0278987 PHOTODETECTOR USING RESONANCE AND RELATED METHOD
A photodetector comprising a contact layer; an absorbing region positioned such that light admitted passes into the absorbing region; a diffractive region...
2017/0278986 SOLAR CELL PANEL
A solar cell panel includes a first solar cell and a second solar cell; and a plurality of leads connecting the first solar cell and the second solar cell....
2017/0278985 SOLAR PANEL ARRAY
A solar energy device includes a solar panel array including a plurality of solar panels, each of the solar panels being divided into solar sub-panels. The...
2017/0278984 UNGUARDED SCHOTTKY BARRIER DIODES
One embodiment of the disclosure relates to an unguarded Schottky barrier diode. The diode includes a cathode that has a recessed region and a dielectric...
2017/0278983 SEMICONDUCTOR DEVICE
A Schottky barrier diode (semiconductor device) includes at least: a semiconductor substrate of an N type (first conductivity type); a semiconductor portion...
2017/0278982 DIODE
A diode includes an n type semiconductor layer including an n type cathode layer and an n type drift layer that has an impurity concentration lower than the n...
2017/0278981 Magnetic Field Sensor Integrated Circuit with Integral Ferromagnetic Material
A magnetic field sensor includes a lead frame, a semiconductor die having a first surface in which a magnetic field sensing element is disposed and a second...
2017/0278980 Method of Manufacturing Thin Film Transistor
Provided is a thin film transistor including an active layer including a first silicon active layer, a second silicon active layer, and an oxide active layer...
2017/0278979 TRANSISTORS INCORPORATING METAL QUANTUM DOTS INTO DOPED SOURCE AND DRAIN REGIONS
Metal quantum dots are incorporated into doped source and drain regions of a MOSFET array to assist in controlling transistor performance by altering the...
2017/0278978 SEMICONDUCTOR DEVICE
To provide a semiconductor device that includes an oxide semiconductor and is miniaturized while keeping good electrical properties. In the semiconductor...
2017/0278977 THIN FILM TRANSISTOR ARRAY PANEL AND METHOD OF MANUFACTURING THE SAME
A thin film transistor array panel includes a substrate; a data line disposed on the substrate; a buffer layer disposed on the substrate and spaced apart from...
2017/0278976 SEMICONDUCTOR DEVICE
A semiconductor device including the following components and a manufacturing method of the semiconductor device are provided. The semiconductor device...
2017/0278975 SEMICONDUCTOR DEVICE
The semiconductor device includes a transistor including an oxide semiconductor film having a channel formation region, a gate insulating film, and a gate...
2017/0278974 THIN FILM TRANSISTOR
A thin film transistor includes an oxide semiconductor layer including a channel region, and a source region and a drain region having a resistivity lower than...
2017/0278973 TRANSISTOR, SEMICONDUCTOR DEVICE, AND ELECTRONIC DEVICE
To provide a semiconductor device with high design flexibility. A first transistor and a second transistor having different electrical characteristics from...
2017/0278972 SEMICONDUCTOR DEVICES, FINFET DEVICES WITH OPTIMIZED STRAINED-SOURECE-DRAIN RECESS PROFILES AND METHODS OF...
Semiconductor devices, FinFET devices with optimized strained-source-drain recess profiles and methods of forming the same are provided. One of the...
2017/0278971 Passivated and Faceted for Fin Field Effect Transistor
A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on...
2017/0278970 FinFET With a Semiconductor Strip as a Base
A method includes forming a first hard mask over a semiconductor substrate, etching the semiconductor substrate to form recesses, with a semiconductor strip...
2017/0278969 SINGLE PROCESS FOR LINER AND METAL FILL
After forming a contact opening in a dielectric material layer located over a substrate, a metal liner layer comprising a nitride of an alloy and a metal...
2017/0278968 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the...
2017/0278967 SEMICONDUCTOR DEVICE INCLUDING MOS TRANSISTOR HAVING SILICIDED SOURCE/DRAIN REGION AND METHOD OF FABRICATING...
A semiconductor device has a silicide source/drain region is fabricated by growing silicon on an epitaxial region including silicon and either germanium or...
2017/0278966 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a substrate including a first active region, a second active region and a field region between the first and second active...
2017/0278965 METHODS FOR FIN THINNING PROVIDING IMPROVED SCE AND S/D EPI GROWTH
Methods to reduce a width of a channel region of Si fins and the resulting devices are disclosed. Embodiments include forming a Si fin in a Si layer; forming a...
2017/0278964 APPARATUS AND METHODS TO CREATE A BUFFER TO REDUCE LEAKAGE IN MICROELECTRONIC TRANSISTORS
Transistor devices having a buffer between an active channel and a substrate, which may include the active channel comprising a low band-gap material on a...
2017/0278963 METHOD AND APPARATUS FOR HIGH VOLTATE TRANSISTORS
A method includes forming a gate spacer along sidewalls of a gate structure, forming a source region and a drain region on opposite sides of the gate...
2017/0278962 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin...
2017/0278961 SEMICONDUCTOR DEVICES WITH AN ENHANCED RESISTIVITY REGION AND METHODS OF FABRICATION THEREFOR
Embodiments of a semiconductor device include a base substrate including an upper surface, a nucleation layer disposed over the upper surface of the base...
2017/0278960 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device including a substrate, a plurality of III-nitride semiconductor layers, a source electrode, a gate electrode, a drain electrode, and a...
2017/0278958 DOUBLE HETEROJUNCTION FIELD EFFECT TRANSISTOR WITH POLARIZATION COMPENSATED LAYER
A semiconductor device includes a substrate, a relaxation layer, a channel layer, a polarization compensation layer, and a barrier layer. The relaxation layer...
2017/0278957 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device according to the present invention includes a channel region of a first conductivity type, disposed at a front surface portion of a...
2017/0278956 SEMICONDUCTOR DEVICE
To improve the performance of a semiconductor device having an IGBT. A p.sup.+-type collector layer is formed on the back surface side of a semiconductor...
2017/0278955 COMPACT DEVICE STRUCTURES FOR A BIPOLAR JUNCTION TRANSISTOR
Device structures for a bipolar junction transistor and methods for fabricating a device structure using a substrate. One or more primary trench isolation...
2017/0278954 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
To reduce a manufacturing cost of a semiconductor device in which a high breakdown voltage transistor and a trench capacitive element in which a part of an...
2017/0278953 METHOD FOR MANUFACTURING MEMORY DEVICE AND METHOD FOR MANUFACTURING SHALLOW TRENCH ISOLATION
A method for manufacturing a memory device includes forming trenches in a substrate to define an active region, filling an insulation material in the trenches,...
2017/0278952 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
A technique of suppressing the potential crowding in the vicinity of the outer periphery of a bottom face of a trench without ion implantation of a p-type...
2017/0278951 VERTICAL TRANSISTORS WITH REDUCED BOTTOM ELECTRODE SERIES RESISTANCE
A semiconductor device includes a source including a first doped semiconductor layer arranged on a substrate, a layer of metal arranged on the first doped...
2017/0278950 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE
A technique of improving the breakdown voltage of a semiconductor device is provided. There is provided a method of manufacturing a semiconductor device...
2017/0278949 STRESS MEMORIZATION AND DEFECT SUPPRESSION TECHNIQUES FOR NMOS TRANSISTOR DEVICES
Disclosed are methods for stress memorization techniques. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating...
2017/0278948 Polysilicon Design for Replacement Gate Technology
The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed...
2017/0278947 SEMICONDUCTOR FIN STRUCTURE AND METHOD OF FORMING THE SAME
A method of forming a semiconductor fin structure is provided. A substrate is provided, which has at least two sub regions and a dummy region disposed...
2017/0278946 FIN SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE WITH SOURCE/DRAIN REGIONS HAVING OPPOSITE CONDUCTIVITIES
A semiconductor device and method of manufacturing a semiconductor device using a semiconductor fin is provided. In an embodiment the fin is formed from a...
2017/0278945 ELECTRONIC DEVICES
A method of manufacturing an electronic device comprising a first terminal (e.g. a source terminal), a second terminal (e.g. a drain terminal), a semiconductor...
2017/0278944 APPARATUS AND METHODS TO CREATE A DOPED SUB-STRUCTURE TO REDUCE LEAKAGE IN MICROELECTRONIC TRANSISTORS
Transistor devices having a doped buffer or sub-structure between an active channel and a substrate. In one embodiment, a p-type dopant, such as magnesium,...
2017/0278943 VERTICAL TRANSISTOR STRUCTURE WITH REDUCED PARASITIC GATE CAPACITANCE
A method of forming a gate spacer in a vertical transistor includes depositing a gate spacer layer on a source layer and a sacrificial gate material on the...
2017/0278942 EXTENDED CONTACT AREA USING UNDERCUT SILICIDE EXTENSIONS
The present invention relates generally to semiconductor devices and more particularly, to a structure and method of forming a contact silicide on a...
2017/0278941 Metal Gate Structure with Device Gain and Yield Improvement
Methods for forming semiconductor structures are disclosed herein. An exemplary method includes forming a gate structure having a dummy gate stack over a...
2017/0278940 MASK, MANUFACTURING METHOD THEREOF AND EXPOSURE SYSTEM
A mask, including a transparent substrate and mask patterns formed on a surface of the transparent substrate, wherein the mask patterns include a first area...
2017/0278939 DUAL METAL INTERCONNECT STRUCTURE
Source/drain contact structures that exhibit low contact resistance and improved electromigration properties are provided. After forming a first contact...
2017/0278938 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor substrate (1) includes a region (AR3) between a region (AR1) and a region (AR2), a control gate electrode (CG) is formed on an upper surface...
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