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Patent # Description
2017/0278836 Integrated System and Method of Making the Integrated System
A system and method of manufacturing a system are disclosed. An embodiment of the system includes a first packaged component comprising a first component and a...
2017/0278835 LED CHIP MOUNTING APPARATUS AND METHOD OF MANUFACTURING DISPLAY APPARATUS BY USING THE LED CHIP MOUNTING APPARATUS
A light emitting diode chip mounting apparatus includes a guide plate including a first surface and a second surface opposite to the first surface, the second...
2017/0278834 METHOD OF MANUFACTURING LIGHT EMITTING ELEMENT AND LIGHT EMITTING DEVICE
A method of manufacturing a light emitting element includes forming a resin film including a phosphor containing layer on a transparent board side surface of a...
2017/0278833 SEMICONDUCTOR PACKAGE
A semiconductor package may include a DRAM chip mounted on a substrate; an interposer stacked over the DRAM chip and including redistribution structures; a...
2017/0278832 SEMICONDUCTOR PACKAGE ASSEMBLY
In one implementation, a semiconductor package assembly includes a first semiconductor package having a first semiconductor die and a first redistribution...
2017/0278831 ARRAY SUBSTRATE OF ORGANIC LIGHT-EMITTING DIODES AND METHOD FOR PACKAGING THE SAME
An array substrate of organic light-emitting diodes and a method for fabricating the same are provided to narrow an edge frame of product device of organic...
2017/0278830 SEMICONDUCTOR PACKAGES HAVING REDUCED STRESS
A semiconductor package comprises a lower package, a metal layer on the lower package, a ground member on the metal layer, coupled thereto, and an upper...
2017/0278829 OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND FLASHLIGHT
Optoelectronic semiconductor component includes at least four different light sources each including at least one optoelectronic semiconductor chip, which...
2017/0278828 Die Stack Assembly Using An Edge Separation Structure For Connectivity Through A Die Of The Stack
A die stack assembly includes first and second power semiconductor device dice. The first die has a P type peripheral edge separation structure that extends...
2017/0278827 PACKAGE-ON-PACKAGE SEMICONDUCTOR DEVICE
Some embodiments relate to a semiconductor device. The semiconductor device includes a substrate. A first die is coupled beneath a lower surface of the...
2017/0278826 SOLID-STATE IMAGE CAPTURING APPARATUS AND ELECTRONIC DEVICE
The present technology relates to a solid-state image capturing apparatus and an electronic device that can acquire a normal image and a narrow band image at...
2017/0278825 Apparatus and Methods for Multi-Die Packaging
A packaged semiconductor device includes a first package substrate having a first plurality of lead fingers, a first die attached to a first major surface of...
2017/0278824 SEMICONDUCTOR MODULE
A semiconductor module (10A) according to one embodiment includes a plurality of first and second transistor chips (hereinafter, first and second transistors)...
2017/0278823 PACKAGE PROCESS AND PACKAGE STRUCTURE
A package structure includes: 1) a circuit substrate; 2) a first semiconductor device disposed on the circuit substrate; 3) a first insulation layer covering a...
2017/0278822 METHOD FOR PRODUCING A SEMI-CONDUCTOR ARRANGEMENT AND CORRESPONDING SEMI-CONDUCTOR ARRANGEMENT
A method for producing a semiconductor arrangement, said method includes fastening a semiconductor on a base element by means of a sintered layer, wherein a...
2017/0278821 OVERLAPPING STACKED DIE PACKAGE WITH VERTICAL COLUMNS
Some forms relate to an electronic assembly (10) that includes a die (11) that includes an upper surface (12) and a conductive column (13) extending from the...
2017/0278820 ANISOTROPIC CONDUCTIVE FILM AND CONNECTION STRUCTURE
An anisotropic conductive film including an electrically insulating adhesive layer, and electrically conductive particles disposed on the electrically...
2017/0278819 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREOF
A semiconductor device includes a board having a solder resist layer with first and second openings on a first surface, and a first electrode on the first...
2017/0278818 HIGH TEMPERATURE SOLDER PASTE
Embodiments herein may relate to a solder paste. The solder paste may include a solder powder and a flux. In embodiments, the flux may be a non-rosin based...
2017/0278817 CHIP ALIGNMENT UTILIZING SUPEROMNIPHOBIC SURFACE TREATMENT OF SILICON DIE
Certain embodiments of the present disclosure provide a method for soldering a chip onto a surface. The method generally includes forming a bonding pad on the...
2017/0278816 VARIABLE BALL HEIGHT ON BALL GRID ARRAY PACKAGES BY SOLDER PASTE TRANSFER
BGA packages with a spatially varied ball height, molds and techniques to form such packages. A template or mold with cavities may be pre-fabricated to hold...
2017/0278815 METAL PILLAR WITH CUSHIONED TIP
A metal pillar with cushioned tip is disclosed. The cushioned tip offsets height difference among metal pillars. So that the height difference among metal...
2017/0278814 SEMICONDUCTOR DEVICES AND SEMICONDUCTOR PACKAGES
A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent...
2017/0278813 PLATING METHOD
A plating method which can achieve a desired dome height is disclosed. The method includes: preparing correlation data showing a relationship between...
2017/0278812 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an...
2017/0278811 SIGNAL TRANSMISSION INSULATIVE DEVICE AND POWER SEMICONDUCTOR MODULE
A signal transmission insulating device includes: a first coil; a second coil opposing the first coil to form a transformer together with the first coil; a...
2017/0278810 EMBEDDED DIE IN PANEL METHOD AND STRUCTURE
Methods for an embedded die panel are disclosed and may include fabricating a first layered structure by: forming first redistribution layers on a first...
2017/0278809 SEMICONDUCTOR STRUCTURE AND FABRICATING METHOD THEREOF
A method of fabricating a semiconductor structure includes: forming a conductive layer on a first insulating layer; etching a portion of the conductive layer...
2017/0278808 ANTENNA CAVITY STRUCTURE FOR INTEGRATED PATCH ANTENNA IN INTEGRATED FAN-OUT PACKAGING
A method for forming an integrated fan-out package includes depositing an adhesive layer on a carrier, forming a back-side buffer layer over the adhesive...
2017/0278807 ELECTRONIC PACKAGE WITH ANTENNA STRUCTURE
Provided is an electronic package, including: a carrier, an electronic component disposed on the carrier, and an antenna structure, wherein the antenna...
2017/0278806 COAXIAL THROUGH VIA WITH NOVEL HIGH ISOLATION CROSS COUPLING METHOD FOR 3D INTEGRATED CIRCUITS
A semiconductor package includes a first semiconductor device, a second semiconductor device vertically positioned above the first semiconductor device, and a...
2017/0278804 ELECTRONIC CIRCUIT PACKAGE
Disclosed herein is an electronic circuit package includes: a substrate having a power supply pattern; an electronic component mounted on a surface of the...
2017/0278803 APPARATUS FOR STACKING SUBSTRATES AND METHOD FOR THE SAME
A substrate stacking apparatus that stacks first and second substrates on each other, by forming a contact region where the first substrate held by a first...
2017/0278802 TEST KEY STRCUTURES, INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING THE SAME
Test key structures, integrated circuit packages and methods of forming the same are disclosed. One of the test key structures includes a first pattern over a...
2017/0278801 HYBRID WAFER DICING APPROACH USING A ROTATING BEAM LASER SCRIBING PROCESS AND PLASMA ETCH PROCESS
Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor...
2017/0278800 HIGH ASPECT RATIO CONTACT METALLIZATION WITHOUT SEAMS
A low resistance middle-of-line interconnect structure is formed without liner layers. A contact metal layer is deposited on source/drain regions of...
2017/0278799 PACKAGE-ON-PACKAGE TYPE PACKAGE INCLUDING INTEGRATED CIRCUIT DEVICES AND ASSOCIATED PASSIVE COMPONENTS ON...
A package-on-package (PoP)-type package includes a first semiconductor package having a first passive element and a first semiconductor device mounted on a...
2017/0278798 SEMICONDUCTOR DEVICE
An object of the present invention is to shorten the switching delay time of a semiconductor device. Transistor units are provided between a source bus line and a...
2017/0278797 Semiconductor Devices Including a Capping Layer
Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and...
2017/0278796 Method for Maximizing Air Gap in Back End of the Line Interconnect through Via Landing Modification
A method of forming an interconnect to an electrical device is provided. The structure produced by the method may include a plurality of metal lines in a...
2017/0278795 ADVANCED E-FUSE STRUCTURE WITH CONTROLLED MICROSTRUCTURE
An advanced e-Fuse structure is described. An e-Fuse device includes an anode region, a cathode region and a fuse element which interconnects the anode and...
2017/0278794 ADVANCED E-FUSE STRUCTURE WITH ENHANCED ELECTROMIGRATION FUSE ELEMENT
A structure for an e-Fuse device in a semiconductor device is described. The e-Fuse device includes an anode region, a cathode region and a fuse element which...
2017/0278793 ADVANCED E-FUSE STRUCTURE WITH HYBRID METAL CONTROLLED MICROSTRUCTURE
A structure of an e-Fuse device in a semiconductor device is described. The e-Fuse device includes an anode region, a cathode region and a fuse element which...
2017/0278792 ADVANCED E-FUSE STRUCTURE WITH ENHANCED ELECTROMIGRATION FUSE ELEMENT
A structure and method for fabricating an e-Fuse device in a semiconductor device is described. A method for fabricating an e-Fuse device includes providing a...
2017/0278791 ADVANCED E-FUSE STRUCTURE WITH HYBRID METAL CONTROLLED MICROSTRUCTURE
A structure and method for fabricating an e-Fuse device in a semiconductor device is described A method for fabricating an e-Fuse device includes providing a...
2017/0278790 ADVANCED E-FUSE STRUCTURE WITH CONTROLLED MICROSTRUCTURE
In one aspect of the invention, a method for fabricating an e-Fuse device is described. A trench structure is provided. The trench structure includes an anode...
2017/0278789 METHOD FOR LAYOUT DESIGN AND STRUCTURE WITH INTER-LAYER VIAS
A computer implemented layout method for an integrated circuit (IC) structure and IC structure are provided. Such a method includes: placing a power supply...
2017/0278788 STRUCTURE AND METHOD FOR MAXIMIZING AIR GAP IN BACK END OF THE LINE INTERCONNECT THROUGH VIA LANDING MODIFICATION
A method of forming an interconnect to an electrical device is provided. The structure produced by the method may include a plurality of metal lines in a...
2017/0278787 MICROELECTRONIC COMPONENTS WITH FEATURES WRAPPING AROUND PROTRUSIONS OF CONDUCTIVE VIAS PROTRUDING FROM...
In a microelectronic component having conductive vias (114) passing through a substrate (104) and protruding above the substrate, conductive features (120E.A,...
2017/0278786 SEMICONDUCTOR DEVICE
A semiconductor device includes a first lower line and a second lower line on a substrate, the first and second lower lines extending in a first direction,...
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