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Patent # Description
2017/0278785 Interconnect Structure for Semiconductor Devices
An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a...
2017/0278784 IMAGING ELEMENT, SOLID-STATE IMAGING DEVICE, AND ELECTRONIC DEVICE
An imaging element includes a layered structural body formed of a first electrode, a light receiving layer formed on the first electrode, and a second...
2017/0278783 MAGNETIC ALIGNMENT FOR FLIP CHIP MICROELECTRONIC DEVICES
Incorporating at least one magnetic alignment structure on a microelectronic device and incorporating at least one alignment coil within a microelectronic...
2017/0278782 ELECTRICAL INTERCONNECT FOR AN INTEGRATED CIRCUIT PACKAGE AND METHOD OF MAKING SAME
An electrical interconnect assembly for use in an integrated circuit package includes a mounting substrate having a thickness defined between a first surface...
2017/0278781 WIRING BOARD
A wiring board of the present disclosure includes a core substrate, insulating layers, signal wiring conductors, ground wiring conductors, power-supply wiring...
2017/0278780 FORMING INTERCONNECT STRUCTURES UTILIZING SUBTRACTIVE PATERNING TECHNIQUES
Methods of forming conductive interconnect structures are described. Those methods/structures may include providing a package substrate comprising a substrate...
2017/0278779 PACKAGE SUBSTRATE WITH EMBEDDED CIRCUIT
A package substrate with embedded circuit is disclosed. The package substrate comprises a redistribution layer, the redistribution layer comprises a plurality...
2017/0278778 MICROELECTRONIC INTERCONNECT ADAPTOR
An interconnect adaptor may be fabricated having a substantially planar surface, to which a microelectronic package may be electrically attached, and a...
2017/0278777 Package Structures and Methods for Forming the Same
A device includes a redistribution line, and a polymer region molded over the redistribution line. The polymer region includes a first flat top surface. A...
2017/0278776 STRUCTURE AND METHOD FOR STABILIZING LEADS IN WIRE-BONDED SEMICONDUCTOR DEVICES
A semiconductor device having a leadframe including a pad (101) surrounded by elongated leads (110) spaced from the pad by a gap (113) and extending to a...
2017/0278775 SEMICONDUCTOR DIES WITH RECESSES, ASSOCIATED LEADFRAMES, AND ASSOCIATED SYSTEMS AND METHODS
Semiconductor dies with recesses, associated leadframes, and associated systems and methods are disclosed. A semiconductor system in accordance with one...
2017/0278774 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor device includes: a semiconductor chip having an electrode on one surface; a first conductive member disposed on one surface side of the...
2017/0278773 WATER-COOLING THERMAL DISSIPATING SYSTEM AND THERMAL DISSIPATIING METHOD
A water-cooling thermal dissipating system includes an electronic device and a thermal dissipating device. The electronic device includes a computing module...
2017/0278772 DIELECTRIC HEAT PATH DEVICES, AND SYSTEMS AND METHODS USING THE SAME
Devices, systems, and methods for dissipating heat generated from an electrical current carrying device are provided herein. The disclosed concept provides a...
2017/0278771 SEMICONDUCTOR DEVICE
A highly-reliable semiconductor device has improved adhesion between a sealing material and a sealed metal member and/or a case member. In some ...
2017/0278770 SEMICONDUCTOR MODULE
An object of the present invention is to provide a semiconductor module with high heat dissipation at a low cost. A semiconductor module according to the...
2017/0278769 CHIP PACKAGE AND METHOD FOR FORMING THE SAME
A chip package includes a chip, a dam layer, a permanent adhesive layer, a support, a buffer layer, a redistribution layer, a passivation layer, and a...
2017/0278768 Packaged device with extended structure for forming an opening in the encapsualant
A packaged device includes an extended structure located at a major side of the packaged device. The extended structure defines an outer area that includes...
2017/0278767 HERMETIC PACKAGE WITH IMPROVED RF STABILITY AND PERFORMANCE
The present disclosure relates to a hermetic package with improved RF stability and performance. The package includes a carrier, a bottom dielectric ring over...
2017/0278766 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a fan-out semiconductor package may include: a first interconnection member having a through-hole; a semiconductor...
2017/0278765 Semiconductor Device and Method of Forming Encapsulated Wafer Level Chip Scale Package (EWLCSP)
A semiconductor device has a semiconductor die and an encapsulant around the semiconductor die. A fan-in interconnect structure is formed over the ...
2017/0278764 Surface Mount Device Package Having Improved Reliability
A semiconductor package for mounting to a printed circuit board (PCB) includes a case comprising a ceramic base, a semiconductor die in the case, a mounting...
2017/0278763 SEMICONDUCTOR DEVICE PACKAGE AND METHODS OF MANUFACTURE THEREOF
A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach...
2017/0278762 Redirecting solder material to visually inspectable package surface
A package comprising an electronic chip, a laminate type encapsulant in and/or on which the electronic chip is mounted, a solderable electric contact on a...
2017/0278761 System and Method for Temperature Control in Plasma Processing System
Techniques herein include systems and methods for fine control of temperature distribution across a substrate. Such techniques can be used to provide uniform...
2017/0278760 Intermediate Structure for Transfer, Method for Preparing Micro-device for Transfer, and Method for Processing...
A method for preparing a plurality of micro-devices for transfer includes temporarily bonding the micro-devices onto a carrier substrate; testing the...
2017/0278759 WORKPIECE EVALUATING METHOD
A workpiece evaluating method evaluates the gettering property of a device wafer having a plurality of devices formed on the front side of the wafer and having...
2017/0278758 METHOD FOR DETECTING BONDING FAILURE PART AND INSPECTION SYSTEM
A method for detecting a bonding failure part of a compound semiconductor chip cut from a compound semiconductor wafer in which a first transparent substrate...
2017/0278757 Methods of Manufacturing Semiconductor Devices
Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes an array having at least one first...
2017/0278756 METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE
A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack, a second gate stack, and a third gate stack,...
2017/0278755 Semiconductor Structures and Methods of Forming the Same
A method of forming a semiconductor structure may include: forming a first dielectric layer having a first thickness over a substrate; removing a first portion...
2017/0278754 METHOD FOR PRODUCING GROUP III NITRIDE CRYSTAL, AND RAMO4 SUBSTRATE
A method for producing a Group III nitride crystal, includes: preparing an RAMO.sub.4 substrate containing a single crystal represented by the general formula...
2017/0278753 GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner...
2017/0278752 SELF-ALIGNED GATE CONTACT
The disclosed technology generally relates to semiconductor devices, and more specifically to electrical contacts to a transistor device, and a method of...
2017/0278750 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
When a MISFET is formed by using a gate last process and replacing dummy gate electrodes with metal gate electrodes, both of respective cap insulating films...
2017/0278749 TUNGSTEN FEATURE FILL
Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as...
2017/0278748 DIRECT PLASMA DENSIFICATION PROCESS AND SEMICONDUCTOR DEVICES
An aspect of the present disclosure relates to a method of forming a barrier layer on a semiconductor device. The method includes placing a substrate into a...
2017/0278747 HIGH PERFORMANCE MIDDLE OF LINE INTERCONNECTS
A method for formation of multi-level contact structures with reduced contact resistance is provided. The contact resistance of the multi-level contact...
2017/0278746 METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE
In a method of manufacturing a semiconductor device, a first insulating interlayer and a sacrificial layer is sequentially formed on a substrate. The...
2017/0278745 OVERLAY MARKS, METHODS OF FORMING THE SAME, AND METHODS OF FABRICATING SEMICONDUCTOR DEVICES USING THE SAME
In a method of fabricating a semiconductor device, a substrate including a circuit area and an overlay mark area is provided. Conductive gate patterns are...
2017/0278744 METHOD OF FORMING TRENCHES WITH DIFFERENT DEPTHS
A method of fabricating a semiconductor device includes forming a first dielectric layer over a substrate that includes a gate structure, forming a first...
2017/0278743 SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREFOR
A method of fabricating a semiconductor device. The method includes forming source/drain features in a substrate on opposite sides of a gate structure, forming...
2017/0278742 Removing Polymer Through Treatment
A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a...
2017/0278741 METHOD OF MANUFACTURING SILICON ON INSULATOR SUBSTRATE
A method of manufacturing a silicon on insulator substrate includes: preparing a semiconductor substrate including a rear side semiconductor layer, an...
2017/0278740 STRUCTURE AND METHOD FOR MAXIMIZING AIR GAP IN BACK END OF THE LINE INTERCONNECT THROUGH VIA LANDING MODIFICATION
A method of forming an interconnect to an electrical device is provided. The structure produced by the method may include a plurality of metal lines in a...
2017/0278739 SEMICONDUCTOR PROCESSING SHEET
The semiconductor processing sheet of the present invention is a semiconductor processing sheet including a base material and a pressure sensitive adhesive...
2017/0278738 ELECTROSTATIC CHUCK DEVICE
An electrostatic chuck device includes: an electrostatic chuck section having one principal surface serving as a placing surface on which a plate-shaped sample...
2017/0278737 PROCESSING APPARATUS FOR WORKPIECE
A processing apparatus has a pedestal which includes an electrostatic chuck and a cooling table. A plurality of heat transfer spaces are provided between the...
2017/0278736 PURGING DEVICE AND PURGING METHOD
Containers are purged between overhead transfer vehicles and a container transfer location to or from which the containers are transferred. A travelling rail...
2017/0278735 METHOD FOR ACQUIRING DATA INDICATING ELECTROSTATIC CAPACITANCE
In a method for acquiring data indicating an electrostatic capacitance between a focus ring and a measuring device includes a disc-shaped base substrate,...
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