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Patent # Description
2017/0288071 THREE-DIMENSIONAL CONDUCTIVE ELECTRODE FOR SOLAR CELL
A photovoltaic device and method include forming a plurality of pillar structures in a substrate, forming a first electrode layer on the pillar structures and...
2017/0288070 TRI-LAYER SEMICONDUCTOR STACKS FOR PATTERNING FEATURES ON SOLAR CELLS
Tri-layer semiconductor stacks for patterning features on solar cells, and the resulting solar cells, are described herein. In an example, a solar cell...
2017/0288069 METHOD OF MANUFACTURING SOLAR CELL MODULE
A method of manufacturing a solar cell module includes: placing a light reflection member across a gap between adjacent two solar cells set on a work table;...
2017/0288068 VOLTAGE BREAKDOWN DEVICE FOR SOLAR CELLS
Voltage breakdown devices for solar cells are described. For example, a solar cell includes a semiconductor substrate. A plurality of alternating N-type and...
2017/0288067 OPTICAL SENSOR SHIELD
Techniques for shielding an optical sensor are described. An example of an electronic device includes an optical sensor and a combined light-focusing and...
2017/0288066 DIODE STRUCTURES WITH CONTROLLED INJECTION EFFICIENCY FOR FAST SWITCHING
This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first...
2017/0288065 Trenched MOS Gate Controlled Rectifier
A trenched MOS gate controlled rectifier has an asymmetric trench structure between the active area of active trenches and the termination area of termination...
2017/0288064 SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE
A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor...
2017/0288063 SEMICONDUCTOR DEVICE
A highly reliable semiconductor device the yield of which can be prevented from decreasing due to electrostatic discharge damage is provided. A semiconductor...
2017/0288062 SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SEMICONDUCTOR DEVICE
A semiconductor device includes an oxide semiconductor film, a first insulating film, and a second insulating film. The oxide semiconductor film is made of...
2017/0288061 SEMICONDUCTOR ELEMENT AND PRODUCTION METHOD FOR SAME
A semiconductor element includes a high-resistivity substrate that includes a .beta.-Ga.sub.2O.sub.3-based single crystal including an acceptor impurity, an...
2017/0288060 THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE AND DISPLAY DEVICE
A TFT is provided. The TFT includes an active layer, and the active layer includes a first active layer and a second active layer. The second active layer is...
2017/0288059 ENHANCED SUBSTRATE CONTACT FOR MOS TRANSISTOR IN AN SOI SUBSTRATE, IN PARTICULAR AN FDSOI SUBSTRATE
An integrated electronic device includes a semiconductive film above a buried insulating layer that is situated above a supporting substrate. An active zone is...
2017/0288058 ELECTROSTATIC DISCHARGE DEVICE
A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to...
2017/0288057 KITE SHAPED CAVITY FOR EMBEDDING MATERIAL
The present invention is directed to semiconductor processes and devices. More specifically, embodiments of the present invention provide a semiconductor...
2017/0288056 FABRICATION OF VERTICAL FIN TRANSISTOR WITH MULTIPLE THRESHOLD VOLTAGES
A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a...
2017/0288054 Lateral MOSFET
A method includes forming a first isolation region in a substrate, wherein a top surface of the first isolation region is level with a top surface of the...
2017/0288053 SEMICONDUCTOR DEVICE
A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper...
2017/0288052 Multiple Shielding Trench Gate FET
A semiconductor device contains a vertical MOS transistor having a trench gate in trenches extending through a vertical drift region to a drain region. The...
2017/0288051 TRENCH MOSFET SHIELD POLY CONTACT
A recess is formed at a semiconductor layer of a device to define a plurality of mesas. An active trench portion of the recess residing between adjacent mesas....
2017/0288050 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR
To improve the breakdown voltage of a semiconductor device. In a terminal region of the semiconductor device, a mesa groove, a recess groove, an electric field...
2017/0288049 METHOD FOR FABRICATING FINFET STRUCTURE
A method of forming a semiconductor device includes providing a substrate structure having a semiconductor substrate and a fin structure on the semiconductor...
2017/0288048 SILICON CARBIDE (SiC) DEVICE WITH IMPROVED GATE DIELECTRIC SHIELDING
In one general aspect, an apparatus can include a silicon carbide (SiC) device can include a gate dielectric, a first doped region having a first conductivity...
2017/0288047 Shallow-Trench Semi-Super-Junction VDMOS Device and Manufacturing Method Therefor
A shallow-trench semi-super-junction VDMOS device and a manufacturing method thereof are disclosed. According to an example of the present invention, the...
2017/0288046 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A property of a semiconductor device (high electron mobility transistor) is improved. A semiconductor device having a buffer layer, a channel layer, an...
2017/0288045 Multichannel Devices with Improved Performance and Methods of Making the Same
A transistor device is provided that comprises a base structure, and a superlattice structure overlying the base structure and comprising a multichannel ridge...
2017/0288044 VERTICAL POWER COMPONENT
A vertical power component includes a doped silicon substrate of a first conductivity type. A local well of a second conductivity type extends from an upper...
2017/0288043 POWER SEMICONDUCTOR DEVICE
A method for forming a power semiconductor device is provided. The method includes providing a substrate having a first surface and a second surface; and...
2017/0288042 METHOD FOR MANUFACTURING A TRANSISTOR
A method comprises arranging a stack, on a semiconductor substrate, comprising a sacrificial layer and an insulating layer. The insulator layer is at least...
2017/0288041 METHOD FOR FORMING A DOPED REGION IN A FIN USING A VARIABLE THICKNESS SPACER AND THE RESULTING DEVICE
A method includes forming a fin in a semiconductor substrate. An isolation structure is formed adjacent the fin. A first portion of the fin extends above the...
2017/0288040 METHOD OF FORMING SIGE CHANNEL FORMATION REGION
A method comprising: forming an SiGe layer on sidewalls of one or more fins of a semiconductor device by a non-selective deposition of amorphous SiGe, the fins...
2017/0288039 FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH
A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to...
2017/0288038 SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes a conductive layer on a source side; a first electrode layer provided on the conductive layer; a second electrode layer...
2017/0288037 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FABRICATING THE SAME
A semiconductor device structure is provided. The semiconductor device includes a semiconductor substrate, a first device, and a second device. Each of the...
2017/0288036 PURE BORON FOR SILICIDE CONTACT
A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench...
2017/0288035 PURE BORON FOR SILICIDE CONTACT
A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench...
2017/0288034 DEVICE STRUCTURE AND MANUFACTURING METHOD USING HDP DEPOSITED SOURCE-BODY IMPLANT BLOCK
This invention discloses a semiconductor power device. The trenched semiconductor power device includes a trenched gate, opened from a top surface of a...
2017/0288033 SHAPED TERMINALS FOR A BIPOLAR JUNCTION TRANSISTOR
Device structure and fabrication methods for a bipolar junction transistor. An emitter layer is formed on a base layer and etched to form an emitter of the...
2017/0288032 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
Provided is a semiconductor device including a gate electrode, source and drain regions, and a spacer. The gate electrode is located over a substrate, and an...
2017/0288031 SELF ALIGNED CONTACT SCHEME
An embodiment is a method including forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls, forming a first hard...
2017/0288030 FABRICATION OF VERTICAL FIELD EFFECT TRANSISTOR STRUCTURE WITH CONTROLLED GATE LENGTH
A method of forming a gate structure, including forming one or more vertical fins on a substrate; forming a bottom spacer on the substrate surface adjacent to...
2017/0288029 THIN FILM TRANSISTOR, METHOD OF MANUFACTURING THIN FILM TRANSISTOR, AND DISPLAY
A thin film transistor includes a gate electrode, an insulation film disposed on the gate electrode, a semiconductor layer facing the gate electrode with the...
2017/0288028 SELF-ALIGNED CONTACT FOR TRENCH POWER MOSFET
Embodiments of the present disclosure provide a self-aligned contact for a trench power MOSFET device. The device has a layer of nitride provided over the...
2017/0288027 METHOD OF FORMING TRENCH SEMICONDUCTOR DEVICE HAVING MULTIPLE TRENCH DEPTHS
A method of forming a semiconductor includes a providing a termination trench and an active trench within a semiconductor layer. The active trench is...
2017/0288026 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a semiconductor layer, having an active region, in which a functional element is formed, a first impurity region of a first...
2017/0288025 SILICON CARBIDE EPITAXIAL SUBSTRATE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE
The silicon carbide layer has a second main surface. The second main surface has a peripheral region within 5 mm from an outer edge thereof, and a central...
2017/0288024 GRADED BUFFER LAYERS WITH LATTICE MATCHED EPITAXIAL OXIDE INTERLAYERS
A lattice matched epitaxial oxide interlayer is disposed between each semiconductor layer of a graded buffer layer material stack. Each lattice matched...
2017/0288023 COMPOSITE OXIDE SEMICONDUCTOR AND METHOD FOR MANUFACTURING THE SAME
The field-effect mobility and reliability of a transistor including an oxide semiconductor film are improved. A semiconductor layer of a transistor is formed...
2017/0288022 GROUP III-N NANOWIRE TRANSISTORS
A group III-N nanowire is disposed on a substrate. A longitudinal length of the nanowire is defined into a channel region of a first group III-N material, a...
2017/0288021 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor layer, having a drain region, a body region, and a source region, a gate electrode, facing the body region via...
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