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Patent # Description
2017/0287918 STATIC RANDOM ACCESS MEMORY (SRAM) DEVICE
To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same...
2017/0287917 EMBEDDED MEMORY WITH ENHANCED CHANNEL STOP IMPLANTS
An integrated circuit contains a logic MOS transistor and a memory MOS transistor of a same polarity. The logic MOS transistor has a logic channel stop layer....
2017/0287916 SEMICONDUCTOR DEVICE
To effectively prevent short circuit between capacitors adjacent to each other. A semiconductor device has a substrate, an interlayer insulating film, a...
2017/0287915 METHOD OF MANUFACTURING CAPACITOR STRUCTURE
A method of manufacturing a semiconductor device includes forming a source/drain region in a substrate. An interlevel dielectric layer is formed on the...
2017/0287914 Method and Apparatus for Forming Boron-Doped Silicon Germanium Film, and Storage Medium
A method for forming a boron-doped silicon germanium film on a base film in a surface of an object to be processed includes: forming a seed layer by adsorbing...
2017/0287913 SEMICONDUCTOR DEVICE WITH METAL GATE
A semiconductor device including a first gate structure is disposed on the semiconductor substrate. The first gate structure includes a gate dielectric layer,...
2017/0287912 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a high voltage NMOS transistor formation region defined by an element isolation insulating film, a CMOS transistor formation...
2017/0287911 MULTI-FINGER DEVICES IN MUTLIPLE-GATE-CONTACTED-PITCH, INTEGRATED STRUCTURES
The present disclosure generally relates to semiconductor structures and, more particularly, to multi-finger devices in multiple-gate-contacted-pitch,...
2017/0287910 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes an isolation layer, first and second fin structures, a gate structure and a source/drain structure. The isolation layer is...
2017/0287909 LAYOUT METHOD AND SEMICONDUCTOR DEVICE
A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and...
2017/0287908 METHOD FOR FORMING DEEP TRENCH ISOLATION FOR RF DEVICES ON SOI
A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a...
2017/0287907 3D CROSS-POINT MEMORY MANUFACTURING PROCESS HAVING LIMITED LITHOGRAPHY STEPS
The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for...
2017/0287906 3D CROSS-POINT MEMORY MANUFACTURING PROCESS HAVING LIMITED LITHOGRAPHY STEPS
The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for...
2017/0287905 MONOLITHIC THREE-DIMENSIONAL (3D) ICs WITH LOCAL INTER-LEVEL INTERCONNECTS
Monolithic 3D ICs employing one or more local inter-level interconnect integrated intimately with at least one structure of at least one transistor on at least...
2017/0287904 CO-FABRICATION OF VERTICAL DIODES AND FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE
A method of forming a vertical finFET and vertical diode device on the same substrate, including forming a channel layer stack on a heavily doped layer;...
2017/0287903 VARIABLE SNUBBER FOR MOSFET APPLICATION
Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically...
2017/0287902 CO-FABRICATION OF VERTICAL DIODES AND FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE
A method of forming a vertical finFET and vertical diode device on the same substrate, including forming a channel layer stack on a heavily doped layer;...
2017/0287901 SEMICONDUCTOR STRUCTURE INCLUDING A TRANSISTOR INCLUDING A GATE ELECTRODE REGION PROVIDED IN A SUBSTRATE AND...
A semiconductor structure includes a bulk semiconductor substrate, an electrically insulating layer over the substrate, an active layer of semiconductor...
2017/0287900 CO-FABRICATION OF VERTICAL DIODES AND FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE
A method of forming a vertical finFET and vertical diode device on the same substrate, including forming a channel layer stack on a heavily doped layer;...
2017/0287898 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE
In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of...
2017/0287897 HIGH VOLTAGE ESD DEVICE FOR FINFET TECHNOLOGY
An ESD protection device includes a semiconductor substrate, first and second fins, first and second doped regions adjacent to each other and having different...
2017/0287896 BIPOLAR SCR
A high-voltage bipolar semiconductor controlled rectifier (SCR) includes an emitter region having a first polarity and overlying a base region having a second...
2017/0287895 ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND APPLICATIONS THEREOF
An ESD protection apparatus includes a semiconductor substrate, a first well, a second well, a first doping region, a second doping region, a third doping...
2017/0287894 DEVICES WITH AN EMBEDDED ZENER DIODE
In one aspect, a silicon-controlled rectifier (SCR) includes a Zener diode embedded in the SCR. In another aspect, a laterally diffused metal oxide...
2017/0287893 ELECTROSTATIC DISCHARGE PROTECTION DEVICE HAVING AN ADJUSTABLE TRIGGERING THRESHOLD
An electrostatic discharge protection device includes first and second diodes series-connected between first and second connection terminals. A third...
2017/0287892 POWER COMPONENT PROTECTED AGAINST OVERHEATING
A triac has a vertical structure formed from a silicon substrate having an upper surface side. A main metallization on the upper surface side has a first...
2017/0287891 Schottky-CMOS Asynchronous Logic Cells
Integrated circuits described herein implement an x-input logic gate. The integrated circuit includes a plurality of Schottky diodes that includes x Schottky...
2017/0287890 SEMICONDUCTOR PACKAGE STRUCTURE
A semiconductor device package is provided. The semiconductor device package includes a first substrate and a conductive element fared on the first substrate....
2017/0287889 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a first chip, a second chip stacked on the first chip, and a third chip stacked on the second chip. The second chip includes a...
2017/0287888 LIGHTING APPARATUSES AND LED MODULES FOR BOTH ILLUMINATION AND OPTICAL COMMUNICATION
An LED module has a controller with a modulator and illumination driver, and first and second LED chains. The first LED chain is connected to the modulator,...
2017/0287887 DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF
A display apparatus including a first substrate including a plurality of light emitting diodes regularly disposed thereon, a second substrate including a...
2017/0287886 WAFER LEVEL PROXIMITY SENSOR
Wafer level proximity sensors are formed by processing a silicon substrate wafer and a silicon cap wafer separately, bonding the cap wafer to the substrate...
2017/0287885 IMPROVED SUBSTRATE FOR SYSTEM IN PACKAGE (SIP) DEVICES
Methods, systems, and devices for enabling the use of a special, generic, or standard substrate for similar system SIP assemblies are disclosed. The required...
2017/0287884 LED LIGHTING APPARATUS
An LED lighting apparatus includes an LED substrate, a LED chip, a sealing resin member, and a reflecting face. The LED substrate has a main surface. The LED...
2017/0287883 LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a light-emitting device includes steps of: preparing at least one substrate having a plurality of through holes; providing an...
2017/0287882 Micro-Transfer Printed LED and Color Filter Structure
A micro-transfer printed intermediate structure comprises an intermediate substrate and one or more pixel structures disposed on the intermediate substrate....
2017/0287881 SEMICONDUCTOR ELEMENT AND MANUFACTURING METHOD THEREOF
A semiconductor element and a manufacturing method thereof are provided. The semiconductor element includes a substrate and multiple semiconductor chips...
2017/0287880 Electronic Device Package Having a Dielectric Layer and an Encapsulant
A method for fabricating an electronic device package includes providing a carrier, disposing a semiconductor chip onto the carrier, the semiconductor chip...
2017/0287879 THIN STACK PACKAGES
The stack package includes a substrate body layer having a top surface and a bottom surface, first circuit patterns disposed on the bottom surface of the...
2017/0287878 HYBRID BOND PAD STRUCTURE
In some embodiments, the present disclosure relates to a multi-dimensional integrated chip having a redistribution structure vertically extending between...
2017/0287877 SEMICONDUCTOR PACKAGE ASSEMBLY
In one implementation, a semiconductor package assembly includes a semiconductor die, a first molding compound covering a back surface of the semiconductor...
2017/0287876 METHOD AND DEVICE FOR CONTROLLING OPERATION USING TEMPERATURE DEVIATION IN MULTI-CHIP PACKAGE
A multi-chip package includes a first die having temperature sensors and a second die. The first die generates temperature deviation information of m (m<n)...
2017/0287875 THREE DIMENSIONAL FULLY MOLDED POWER ELECTRONICS MODULE HAVING A PLURALITY OF SPACERS FOR HIGH POWER APPLICATIONS
A power electronic package includes a first substrate, a second substrate oppositely disposed from the first substrate, one or more chips disposed between the...
2017/0287874 STACKED CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A stacked chip package structure includes a first chip, pillar bumps, a first encapsulant, a first redistribution layer, a second chip, a second encapsulant, a...
2017/0287873 ELECTRONIC ASSEMBLY COMPONENTS WITH CORNER ADHESIVE FOR WARPAGE REDUCTION DURING THERMAL PROCESSING
An IC package, an electronic assembly, and methods of preventing warpage of components of an electronic assembly during fabrication of the electronic assembly...
2017/0287872 BUMPLESS WAFER LEVEL FAN-OUT PACKAGE
An integrated circuit package may include a first conductive pad on an interposer substrate, and a second conductive pad formed on a front surface of an...
2017/0287871 SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor package structure includes a conductive structure, a semiconductor element disposed on and electrically connected to the conductive structure,...
2017/0287870 STACKED CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A stacked chip package structure includes a first chip, stud bumps, a second chip, pillar bumps, an encapsulant and conductive vias. The first stud bumps are...
2017/0287869 WIRE CONNECTING METHOD AND TERMINAL
A method of connecting a wire with a terminal including a plurality of conductors is provided. The method includes: positioning the terminal by holding a part...
2017/0287868 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A pad formed in a semiconductor chip is formed such that a thickness of an aluminum film in a wire bonding portion is smaller than that of an aluminum film in...
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