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Patent # Description
2017/0301682 ERASABLE PROGRAMMABLE NON-VOLATILE MEMORY
An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor...
2017/0301681 CONFIGURABLE ROM
A configurable read only memory (ROM) including a number of memory cells. The memory cells include first-type memory cells that are electrically-programmable...
2017/0301680 METAL FINFET ANTI-FUSE
Semiconductor structures containing FinFET anti-fuses with reduced breakdown voltage are provided which can be readily integrated with high performance...
2017/0301679 METHOD FOR PRODUCING AN SGT-INCLUDING SEMICONDUCTOR DEVICE
A method for producing an SGT-including semiconductor device includes forming a gate insulating layer on an outer periphery of a Si pillar, forming a gate...
2017/0301678 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
In an image information chip or the like, a multi-port SRAM is embedded with a logic circuit. When the 3 port is used, the 1 port may serve as a differential...
2017/0301677 NANO-IMPRINTED SELF-ALIGNED MULTI-LEVEL PROCESSING METHOD
The present disclosure generally relates to fine geometry electrical circuits and methods of manufacture thereof. More specifically, methods for forming 3D...
2017/0301676 SEMICONDUCTOR DEVICE, METHOD OF FABRICATING THE SAME, AND APPARATUS USED IN FABRICATION THEREOF
A semiconductor device includes a substrate, upper impurity regions in upper portions of the substrate, metal electrodes electrically connected to the upper...
2017/0301675 ULTRA HIGH DENSITY INTEGRATED COMPOSITE CAPACITOR
Capacitors that can be formed fully on an integrated circuit (IC) chip are described in this disclosure. An IC chip includes a metal-oxide-silicone (MOS)...
2017/0301674 Three-Dimensional Vertical One-Time-Programmable Memory
The present invention discloses a three-dimensional vertical read-only memory (3D-OTP.sub.V). It comprises a plurality of vertical OTP strings formed...
2017/0301673 HIGH VOLTAGE CMOS WITH TRIPLE GATE OXIDE
An integrated circuit containing a first plurality of MOS transistors operating in a low voltage range, and a second plurality of MOS transistors operating in...
2017/0301672 SUB 59 MV / DECADE SI CMOS COMPATIBLE TUNNEL FET AS FOOTER TRANSISTOR FOR POWER GATING
An integrated circuit (IC) including a circuit block including a plurality of complementary metal oxide semiconductor field-effect transistors (CMOSFETs), and...
2017/0301671 FIN PITCH SCALING FOR HIGH VOLTAGE DEVICES AND LOW VOLTAGE DEVICES ON THE SAME WAFER
A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second...
2017/0301670 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A method for fabricating semiconductor device includes the steps of: providing a substrate having a gate structure thereon; forming a silicon layer on the...
2017/0301669 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
To provide a semiconductor device having an element isolation structure formed in the main surface of semiconductor substrate, having a space in a trench, and...
2017/0301668 INTEGRATED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a substrate including a first region and a second region, a first transistor and a second transistor formed in the first region...
2017/0301667 3D SEMICONDUCTOR STRUCTURE AND DEVICE
A 3D structure, the structure including: a first stratum overlaid by a second stratum, the second stratum is less than two microns thick, where the first...
2017/0301666 LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE INTEGRATED WITH VERTICAL FIELD EFFECT TRANSISTOR
An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal...
2017/0301665 SEMICONDUCTOR DEVICE AND DESIGN METHOD OF SAME
A semiconductor device includes a semiconductor substrate having a predetermined region in which a standard cell is disposed, and also includes: a first...
2017/0301664 SEMICONDUCTOR DEVICE
Based on a basic idea to effectively utilize a space created in a third wiring layer (M3) by a zero-th wiring layer (M0) which can exist by miniaturization of...
2017/0301663 MECHANISMS FOR FORMING PACKAGE STRUCTURE
A package structure is provided. The package structure includes a semiconductor die and a protection layer surrounding sidewalls of the semiconductor die. The...
2017/0301662 POWER CONVERSION APPARATUS
A power conversion apparatus performs power conversion. The power conversion apparatus includes a semiconductor module and a cooler. The semiconductor module...
2017/0301661 OPTICAL APPARATUS
An optical apparatus includes a substrate 1, a wiring pattern 8 formed on the substrate 1, a light-receiving element 3 and a light-emitting element 2 provided...
2017/0301660 METHOD OF FORMING AN ARRAY OF A MULTI-DEVICE UNIT CELL
Backplane-side bonding structures including a common metal are formed on a backplane. Multiple source coupons are provided such that each source coupon...
2017/0301658 FABRICATION METHOD OF PACKAGE STRUCTURE
A method for fabricating a package structure is provided, which includes the steps of: providing a carrier having a plurality of bonding pads; laminating a...
2017/0301657 THREE DIMENSIONAL INTEGRATED CIRCUIT
A method comprises providing a first substrate having dielectric structures and conductive structures. Ions are implanted into the first substrate, the ions...
2017/0301656 HETEROGENEOUS ANNEALING METHOD AND DEVICE
A method of integrating a first substrate having a first surface with a first insulating material and a first contact structure with a second substrate having...
2017/0301655 REDUCED FORM FACTOR RADIO FREQUENCY SYSTEM-IN-PACKAGE
A packaged module for a radio frequency wireless device has a substrate supporting a first wireless device component and a second wireless device component...
2017/0301654 SYSTEM IN PACKAGE WITH VERTICALLY ARRANGED RADIO FREQUENCY COMPONENTRY
A packaged module for use in a wireless communication device has a substrate supporting a first integrated circuit die that implements at least a portion of a...
2017/0301653 RADIO FREQUENCY SYSTEM-IN-PACKAGE WITH STACKED CLOCKING CRYSTAL
A packaged module for use in a wireless communication device has a substrate supporting a crystal and a first die that includes at least a microprocessor and...
2017/0301652 METHOD OF FABRICATING PACKAGE SUBSTRATES
This disclosure provides a package substrate fabrication method including: forming a first conductive wire and a first connecting unit on a first carrier...
2017/0301651 WAFER LEVEL SYSTEM IN PACKAGE (SIP) USING A RECONSTITUTED WAFER AND METHOD OF MAKING
A package such as a system in package (SiP) includes a first die disposed in a first mold layer and coupled to a first dielectric layer disposed above the...
2017/0301650 3DIC Formation with Dies Bonded to Formed RDLs
A method includes forming a dielectric layer over a carrier, forming a plurality of bond pads in the dielectric layer, and performing a planarization to level...
2017/0301649 Chip Packages and Methods of Manufacture Thereof
Chip packages and method of manufacturing the same are disclosed. In an embodiment, a chip package may include: a redistribution layer (RDL); a first chip...
2017/0301648 Methods and Structures for Packaging Semiconductor Dies
A method of packaging a semiconductor device, comprising: attaching a plurality of dies to a carrier wafer, wherein each of the dies includes a top surface;...
2017/0301647 RADIO FREQUENCY TRANSMISSION LINE WITH FINISH PLATING ON CONDUCTIVE LAYER
This disclosure relates to a radio frequency (RF) transmission line for high performance RF applications. The RF transmission line includes a conductive layer...
2017/0301646 METHOD OF BONDING SEMICONDUCTOR SUBSTRATES
The disclosed technology generally relates to semiconductor wafer bonding, and more particularly to direct bonding by contacting surfaces of the semiconductor...
2017/0301645 Method and Apparatus for Connecting Packages onto Printed Circuit Boards
Methods and apparatus are disclosed for attaching the integrated circuit (IC) packages to printed circuit boards (PCBs) to form smooth solder joints. A polymer...
2017/0301644 CLAMPING SYSTEM, WIRE BONDING MACHINE, AND METHOD FOR BONDING WIRES
A clamping system, a wire bonding machine and a method for bonding wires are provided. An exemplary clamping system includes a clamping device. The clamping...
2017/0301643 SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second...
2017/0301642 PRINTED WIRING BOARD
A printed wiring board according to an embodiment includes a metal plate and a wiring member. The meal plate includes a current path part, which is a main...
2017/0301641 Three-Dimensional Chip Stack and Method of Forming the Same
A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection...
2017/0301640 SEMICONDUCTOR DEVICE WITH A SEMICONDUCTOR CHIP CONNECTED IN A FLIP CHIP MANNER
A semiconductor device includes a wiring board, a semiconductor chip, and a connecting member provided between a surface of the wiring board and a functional...
2017/0301639 MICROELECTRONIC DEVICES AND METHODS FOR FILLING VIAS IN MICROELECTRONIC DEVICES
Microelectronic devices and methods for filling vias and forming conductive interconnects in microfeature workpieces and dies are disclosed herein. In one...
2017/0301638 INTERCONNECT ETCH WITH POLYMER LAYER EDGE PROTECTION
Various semiconductor workpiece polymer layers and methods of fabricating the same are disclosed. In one aspect, a method of manufacturing is provided that...
2017/0301637 Contact Pad For Semiconductor Device
A device and method of manufacture is provided that utilize a dummy pad feature adjacent contact pads. The contact pads may be contact pads in an integrated...
2017/0301636 ELECTROSTATIC DISCHARGE PROTECTION FOR ANTENNA USING VIAS
An integrated circuit device is formed to include a plurality of vias that connect an antenna to a ground reference. This configuration of the integrated...
2017/0301635 ELECTRONIC CHIP
An electronic chip including: a plurality of first semiconductor bars of a first conductivity type and of second semiconductor bars of a second conductivity...
2017/0301634 SEMICONDUCTOR APPARATUS WITH FAKE FUNCTIONALITY
A semiconductor apparatus with fake functionality includes a logic device and at least one fake device. The logic device is formed on a substrate and turned on...
2017/0301633 Power Module and Power Conversion Apparatus
An object of the present invention is to provide a power module that secures a heat dissipation route and has increased reliability. A power module of the...
2017/0301632 PACKAGE AND METHOD OF MANUFACTURING THE SAME
The method of manufacturing a package comprising: preparing a strip substrate having a plurality of separate package regions which are partitioned by a dicing...
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