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Patent # Description
2017/0301631 VERTICAL INTERCONNECTS FOR SELF SHIELDED SYSTEM IN PACKAGE (SiP) MODULES
A system in package (SiP) is disclosed that uses an EMI shield to inhibit EMI or other electrical interference on the components within the SiP. A metal shield...
2017/0301630 METHODS FOR SELECTIVELY SHIELDING RADIO FREQUENCY MODULES
Aspects of this disclosure relate to methods of selectively shielded radio frequency modules. A radio frequency module can be provided with a radio frequency...
2017/0301629 SEMICONDUCTOR PACKAGE HAVING A METAL PAINT LAYER
Disclosed are devices and methods related to a conductive paint layer configured to provide radio-frequency (RF) shielding for a packaged semiconductor module....
2017/0301628 ELECTRONIC CIRCUIT PACKAGE
Disclosed herein is an electronic circuit package includes: a substrate having a power supply pattern; an electronic component mounted on a surface of the...
2017/0301627 LINE STRUCTURE AND A METHOD FOR PRODUCING THE SAME
A multi-layer line structure including a substrate, a lower layer Cu line located on the substrate, an upper layer Cu line located on an insulating layer...
2017/0301626 EMBEDDED COMPONENT PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME
An embedded component package structure includes a substrate. A first conductive component extends from a first surface of the substrate to a second surface of...
2017/0301625 INTEGRATED CIRCUIT PACKAGE WITH EMBEDDED BRIDGE
Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output...
2017/0301624 SELECTIVE AND NON-SELECTIVE BARRIER LAYER WET REMOVAL
A method for manufacturing a semiconductor device includes forming a dielectric layer on a substrate, forming a plurality of openings in the dielectric layer,...
2017/0301623 STACK OF LAYERS FOR PROTECTING AGAINST A PREMATURE BREAKDOWN OF INTERLINE POROUS DIELECTRICS WITHIN AN...
A stack including a dual-passivation is etched locally so as to reveal contact pads of an integrated circuit which are situated above a last metallization...
2017/0301622 III-V COMPATIBLE ANTI-FUSES
An anti-fuse is provided above a semiconductor material. The anti-fuse includes a first end region including a first metal structure; a second end region...
2017/0301621 AIRGAP PROTECTION LAYER FOR VIA ALIGNMENT
A method for via alignment includes forming first airgaps between interconnect structures and depositing a pinch off layer to close off openings to the first...
2017/0301620 STRUCTURE AND PROCESS FOR METAL CAP INTEGRATION
The disclosure relates to semiconductor interconnect structure having enhanced electromigration (EM) reliability in which an oxygen scavenger layer deposited...
2017/0301619 INTEGRATED CIRCUIT SURFACE LAYER WITH ADHESION-FUNCTIONAL GROUP
Embodiments of the present disclosure describe an integrated circuit and associated fabrication techniques and configurations, which may include forming on at...
2017/0301618 Advanced Metal Connection With Metal Cut
Examples of an integrated circuit a having an advanced two-dimensional (2D) metal connection with metal cut and methods of fabricating the same are provided....
2017/0301617 LEADFRAME SUBSTRATE WITH ISOLATOR INCORPORATED THEREIN AND SEMICONDUCTOR ASSEMBLY AND MANUFACTURING METHOD THEREOF
The leadframe substrate includes an isolator incorporated with metal leads by a compound layer. The metal leads are disposed about sidewalls of the isolator...
2017/0301616 Body-Mountable Device with a Common Substrate for Electronics and Battery
An example device includes a silicon substrate having a first substrate surface and a second substrate surface; a plurality of layers associated with one or...
2017/0301615 SEMICONDUCTOR DEVICE THAT INCLUDES A MOLECULAR BONDING LAYER FOR BONDING OF ELEMENTS
A semiconductor device includes a semiconductor chip having a terminal thereon, a lead frame for connection to an external device, a bonding wire connecting...
2017/0301614 SEMICONDUCTOR MODULE
A semiconductor module of an electric power converter includes an IGBT and a MOSFET which are connected in parallel to each other and provided on the same lead...
2017/0301613 Adaptable Molded Leadframe Package and Related Method
A semiconductor package includes at least one semiconductor device situated on a leadframe island, a first at least one lead protruding from a first side of...
2017/0301612 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device includes a plurality of islands, each having an outer surface including an upper surface and end surfaces, semiconductor chips, above...
2017/0301611 METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE COMPRISING A SEMICONDUCTOR DEVICE LAYER FORMED ON A...
The present disclosure provides a semiconductor structure, including: a semiconductor device layer including a first surface and a second surface, wherein the...
2017/0301610 COOLER MODULE, AND METHOD FOR MANUFACTURING COOLER MODULE
A cooler module has a cooling tube and a support member. The cooling tube has a first protruding tube portion and a second protruding tube portion. The first...
2017/0301609 POWER ELECTRONICS MODULE
A power electronics module is provided having one or more power converter semiconductor components. The power electronics module further has a substrate having...
2017/0301608 Wafer Level Embedded Heat Spreader
Disclosed herein are a device having an embedded heat spreader and method for forming the same. A carrier substrate may comprise a carrier, an adhesive layer,...
2017/0301607 COOLING OF WIDE BANDGAP SEMICONDUCTOR DEVICES
A power device comprises at least one power semiconductor module comprising a wide bandgap semiconductor element; and a cooling system for actively cooling the...
2017/0301606 BIDIRECTIONAL SEMICONDUCTOR PACKAGE
Provided is a bidirectional semiconductor package in which the number of processes for manufacturing the bidirectional semiconductor package is reduced....
2017/0301605 EMBEDDING DIAMOND AND OTHER CERAMIC MEDIA INTO METAL SUBSTRATES TO FORM THERMAL INTERFACE MATERIALS
A multi-layer structure includes a substrate with a surface and with particles partially covering and partially embedded in the surface. The particles have...
2017/0301604 SEMICONDUCTOR DEVICE
A semiconductor device according to the present disclosure includes an electrically conductive first electrode block, an electrically conductive submount, an...
2017/0301603 SEMICONDUCTOR DEVICE
A semiconductor device includes a base plate, a case, a power semiconductor element, and a control semiconductor element. Case is provided on base plate. Power...
2017/0301602 HEAT DISSIPATION STRUCTURE OF SEMICONDUCTOR DEVICE
A heat dissipation structure of a semiconductor device with excellent heat dissipation applicable to surface-mount thin semiconductor devices is provided, and...
2017/0301601 Trench-type heat sink structure applicable to semiconductor device
The present invention discloses a trench-type heat sink structure applicable to semiconductor devices. An embodiment of the present invention comprises: a...
2017/0301600 POWER ELECTRONICS ARRANGEMENT AND VEHICLE WITH SAID ARRANGEMENT
A power electronics arrangement has a power semiconductor module, with a contact spring, with a load connecting element and with a mounting device which is...
2017/0301599 SEMICONDUCTOR DEVICE
A semiconductor device includes a lead frame; a circuit board located on the lead frame; a power device that includes a switching element and is mounted on the...
2017/0301598 MICROELECTRONIC DEVICES, STACKED MICROELECTRONIC DEVICES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES
Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set...
2017/0301597 THERMOSETTING RESIN COMPOSITION AND METHOD OF PRODUCING SAME
Provided is a thermosetting resin composition, which can be used as underfill for obtaining favorable solder connectivity while suppressing the formation of...
2017/0301596 SILICON PACKAGE FOR EMBEDDED SEMICONDUCTOR CHIP AND POWER CONVERTER
A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second...
2017/0301595 SILICON PACKAGE FOR EMBEDDED SEMICONDUCTOR CHIP AND POWER CONVERTER
A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second...
2017/0301594 SEMICONDUCTOR MODULE
A semiconductor module includes a rectangular base plate; a substrate which is placed on the base plate and on which a circuit including a semiconductor chip...
2017/0301593 METHOD FOR PRODUCING A PLURALITY OF MEASUREMENT REGIONS ON A CHIP, AND CHIP WITH MEASUREMENT REGIONS
A chip and a method for producing the chip with a plurality of measurement regions which are provided with electrodes for electrically detecting reactions in...
2017/0301592 WAFER PROCESSING METHOD
There is provided a wafer processing method for dividing a wafer having a plurality of devices formed in regions partitioned by a plurality of crossing...
2017/0301591 X-RAY SYSTEM, SEMICONDUCTOR PACKAGE, AND TRAY HAVING X-RAY ABSORPTION FILTER
An X-ray source is disposed and a detector is disposed adjacent to the X-ray source. A test specimen holder is disposed between the X-ray source and the...
2017/0301590 LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE INTEGRATED WITH VERTICAL FIELD EFFECT TRANSISTOR
An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal...
2017/0301589 METHODS OF FORMING NMOS AND PMOS FINFET DEVICES AND THE RESULTING PRODUCT
A method includes forming an initial strain relaxed buffer layer on a semiconductor substrate. A trench is formed within the initial strain relaxed buffer...
2017/0301588 Structure and Method for FinFET Device
The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate...
2017/0301587 RECONFIGURABLE SEMICONDUCTOR DEVICE
A reconfigurable device and an analog circuit are formed on a single chip so that the analog circuit can be controlled by the reconfigurable device. A...
2017/0301586 FINFET SWITCH
An embodiment of a semiconductor switch structure includes source contacts, drain contacts, gates and fins. The contacts and gates are elongated in a first...
2017/0301585 METHOD FOR CREATING THROUGH-CONNECTED VIAS AND CONDUCTORS ON A SUBSTRATE
A method to reduce the number and type of processing steps to achieve conductive lines in the planes of a substrate concurrently interconnecting conductor...
2017/0301584 METHOD AND APPARATUS FOR SINGLE CHAMBER TREATMENT
The disclosure relates to using a single chamber for multiple treatments resulting in a semiconductor chip having an interconnect. An exemplary process many...
2017/0301583 METHOD FOR PRODUCING AN INTEGRATED CIRCUIT INCLUDING A METALLIZATION LAYER COMPRISING LOW K DIELECTRIC MATERIAL
A method of forming a metallization layer of an IC having a lower via level and an upper trench level is disclosed. In one aspect, the method includes applying...
2017/0301582 METHOD FOR MANUFACTURING BONDED WAFER
A method for manufacturing a bonded wafer using a base wafer which is an epitaxial wafer produced by a method including at least one of: (1) setting a chamfer...
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