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Patent # Description
2017/0309656 IMAGE SENSOR WITH SOLAR CELL FUNCTION AND ELECTRONIC DEVICE THEREOF
A unit pixel element that acts as an image sensor or a solar cell according to the present invention comprises a photo detector that drives a photocurrent...
2017/0309655 IMAGE SENSOR WITH SOLAR CELL FUNCTION
A unit pixel element that acts as an image sensor or a solar cell according to the present invention comprises a photo detector that drives a photocurrent...
2017/0309654 Display Substrate and Manufacturing Method Thereof, Display Apparatus
The present disclosure provides a display substrate and a manufacturing method thereof, and a display apparatus, the manufacturing method comprises: forming a...
2017/0309653 TFT BACKPLATE STRUCTURE COMPRISING TRANSISTORS HAVING GATE ISOLATION LAYERS OF DIFFERENT THICKNESSES AND...
A includes a switch TFT and a drive TFT. The switch TFT is formed of a first source and a first drain, a first gate, and a first etching stopper layer, and a...
2017/0309652 FLEXIBLE DISPLAY PANEL AND DISPLAY DEVICE
The present disclosure relates provide a flexible display panel and a display device. The flexible display panel includes: a flexible substrate; an inorganic...
2017/0309651 DISPLAY DEVICE
A display device includes a substrate including a display area to display an image and a non-display area provided on at least one side of the display area, a...
2017/0309650 SEMICONDUCTOR DEVICE
A semiconductor device which includes an oxide semiconductor and in which formation of a parasitic channel due to a gate BT stress is suppressed is provided....
2017/0309649 THIN FILM TRANSISTOR SUBSTRATE, METHOD FOR MANUFACTURING THIN FILM TRANSISTOR SUBSTRATE, AND DISPLAY PANEL
A thin film transistor substrate includes: a substrate; and a first thin film transistor and a second thin film transistor that are disposed on the substrate....
2017/0309648 ARRAY SUBSTRATE OF DISPLAY PANEL
An array substrate of display panel comprises a substrate, a first and second transistors disposed on the substrate. The first and second transistors are...
2017/0309647 STRUCTURE AND METHOD TO FORM DEFECT FREE HIGH-MOBILITY SEMICONDUCTOR FINS ON INSULATOR
A semiconductor structure is provided that includes a plurality of high mobility semiconductor material (i.e., silicon germanium alloy of III-V compound...
2017/0309646 DISPLAY DEVICE AND METHOD FOR MANUFACTURING SAME
A display device includes a display panel divided into a display region and a non-display region, the display panel including a panel pad part on the...
2017/0309645 DUAL DATA STRUCTURE FOR HIGH RESOLUTION AND REFRESH RATE
Display backplanes and pixel element structures are described. In an embodiment, a pixel electrode is located between two stacked data lines, with a left edge...
2017/0309644 DISPLAY DEVICE
The display device includes a display area, a non-display area, pixel structures, gate lines, data lines, first fan-out conductive lines, second fan-out...
2017/0309643 TUNABLE CAPACITOR FOR FDSOI APPLICATIONS
A semiconductor device includes an SOI substrate having a base substrate material, an active semiconductor layer positioned above the base substrate material...
2017/0309641 SEMICONDUCTOR APPARATUS WITH MULTIPLE TIERS, AND METHODS
Apparatus and methods are disclosed, including an apparatus that includes a number of tiers of a first semiconductor material, each tier including at least one...
2017/0309640 NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
A nonvolatile memory device includes gate electrodes three dimensionally arranged on a semiconductor substrate, a semiconductor pattern extending from the...
2017/0309639 THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
An electrode structure includes a plurality of electrodes vertically stacked on a substrate. Each of the plurality of electrodes includes an electrode portion,...
2017/0309638 SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME
A semiconductor memory device includes a first semiconductor layer; a stacked body including a plurality of electrode layers stacked in a first direction; a...
2017/0309637 SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
A semiconductor device and a method of forming the same are provided. The semiconductor device includes interlayer support patterns sequentially stacked on a...
2017/0309636 MANUFACTURING METHOD OF MEMORY DEVICE
A method of manufacturing a memory device includes providing a semiconductor substrate including a first region and a second region. The method includes...
2017/0309635 MEMORY DEVICES HAVING COMMON SOURCE LINES INCLUDING LAYERS OF DIFFERENT MATERIALS
A memory device includes a gate structure including a plurality of gate electrode layers stacked on an upper surface of a substrate, a plurality of channel...
2017/0309634 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD FOR SAME
A semiconductor memory device comprises a memory block including conductive layers at different levels from a substrate and separated from each other by a...
2017/0309633 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
Stack structures are arranged in a first direction horizontal to a semiconductor substrate, one of which has a longitudinal direction along a second direction....
2017/0309632 PILLAR-SHAPED SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR PRODUCING THE SAME
An SRAM includes three Si pillars. In upper parts of the Si pillars, a first load P-channel, a first driver N-channel, and a first selection N-channel are...
2017/0309631 FLIPPED VERTICAL FIELD-EFFECT-TRANSISTOR
Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an...
2017/0309630 FLIPPED VERTICAL FIELD-EFFECT-TRANSISTOR
Various embodiments disclose a method for fabricating vertical transistors. In one embodiment, a structure is formed comprising at least a first substrate, an...
2017/0309629 Semiconductor Device and Fabricating the Same
An integrated circuit (IC) device comprises a substrate having a metal-oxide-semiconductor (MOS) region; a gate region disposed over the substrate and in the...
2017/0309628 FINFET DEVICE WITH ENLARGED CHANNEL REGIONS
A method of manufacturing a semiconductor device includes providing a semiconductor layer, forming a plurality of semiconductor fins on a surface of the...
2017/0309627 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from...
2017/0309626 FORMING GATES WITH VARYING LENGTH USING SIDEWALL IMAGE TRANSFER
A chip includes multiple first transistors in a first region and multiple second transistors in a second region. A gap between adjacent first transistors has a...
2017/0309625 Integrated Circuit Devices
An integrated circuit device includes a fin-type active area extending on a substrate in a first direction, a first gate line and a second gate line extending...
2017/0309624 FINFETS AND METHODS OF FORMING FINFETS
An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation...
2017/0309623 METHOD, APPARATUS, AND SYSTEM FOR INCREASING DRIVE CURRENT OF FINFET DEVICE
We disclose semiconductor devices, comprising a semiconductor substrate comprising bulk silicon; and a plurality of fins formed on the semiconductor substrate;...
2017/0309622 FORMING GATES WITH VARYING LENGTH USING SIDEWALL IMAGE TRANSFER
Semiconductor devices and methods of forming the same include forming mandrels on a first region and a second region of a gate layer. First spacers are formed...
2017/0309621 SEMICONDUCTOR DEVICE HAVING GATE STRUCTURE WITH REDUCED THRESHOLD VOLTAGE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device is provided, including: a substrate having a first area and a second area; several first gate structures formed at the first area, and...
2017/0309620 BIPOLAR JUNCTION TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
A bipolar junction transistor having a relatively reduced size and an improved current gain and a method of manufacturing the same are disclosed. The bipolar...
2017/0309619 SEMICONDUCTOR DEVICE COMPRISING TRANSISTOR CELL UNITS WITH DIFFERENT THRESHOLD VOLTAGES
An embodiment of a semiconductor device comprises a transistor cell array in a semiconductor body. The transistor cell array comprises transistor cell units....
2017/0309618 BIPOLAR JUNCTION TRANSISTOR DEVICE HAVING BASE EPITAXY REGION ON ETCHED OPENING IN DARC LAYER
A method is provided of forming a bipolar transistor device. The method comprises depositing a collector dielectric layer over a substrate in a collector...
2017/0309617 CASCODE SEMICONDUCTOR DEVICE STRUCTURE AND METHOD THEREFOR
In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor...
2017/0309616 LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE INTEGRATED WITH VERTICAL FIELD EFFECT TRANSISTOR
An electrical device that in some embodiments includes a substrate including a lateral device region and a vertical device region. A lateral diffusion metal...
2017/0309615 METHOD, APPARATUS, AND SYSTEM FOR METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR (MOSFET) WITH ELECTROSTATIC...
Methods, apparatus, and systems relating to a MOSFET with ESD resistance, specifically, to a semiconductor device comprising a field-effect transistor (FET)...
2017/0309614 ENHANCED LAYOUT OF MULTIPLE-FINGER ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE
An enhanced layout for a multiple-finger ESD protection device has several embodiments. In these embodiments, the base contacts of the NPN (or PNP) transistors...
2017/0309613 ELECTROSTATIC DISCHARGE PROTECTION SEMICONDUCTOR DEVICE AND LAYOUT STRUCTURE OF ESD PROTECTION SEMICONDUCTOR DEVICE
A layout structure of an ESD protection semiconductor device includes a substrate, a first doped region, a pair of second doped regions, a pair of third doped...
2017/0309612 SILICON CONTROLLED RECTIFIER
A silicon controlled rectifier including a semiconductor substrate, first and second semiconductor wells, first and second semiconductor regions, third and...
2017/0309611 FORMING A SELF-ALIGNED SINGLE DIFFUSION BREAK (SDB) ISOLATION STRUCTURE IN A GATE REGION OF A DIODE FOR REDUCED...
Aspects for forming a self-aligned single diffusion break (SDB) isolation structure in a gate region of a diode for reduced capacitance, resistance, and/or...
2017/0309610 RECTIFICATION DEVICE, METHOD FOR MANUFACTURING THE SAME AND ESD PROTECTION DEVICE
Disclosed is a rectification device, a method for manufacturing the same and an ESD protection device. The rectification device comprises: a semiconductor...
2017/0309609 Methods for Linewidth Modification and Apparatus Implementing the Same
A linear-shaped core structure of a first material is formed on an underlying material. A layer of a second material is conformally deposited over the...
2017/0309608 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE
A semiconductor device and a fabricating method of semiconductor device are disclosed. The semiconductor device comprises: a substrate having a bonding pad on...
2017/0309607 METHOD FOR EMBEDDING SILICON DIE INTO A STACKED PACKAGE
Several embodiments of microelectronic configurations with logic components and associated methods of manufacturing are disclosed herein. In one embodiment,...
2017/0309606 MODULE SUBSTRATE AND SEMICONDUCTOR MODULE
In one embodiment, the semiconductor module includes a module substrate and a first substrate mounted on and electrically connected to a first surface of the...
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