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Patent # Description
2017/0309351 METHOD AND APPARATUS FOR PERIODIC ION COLLISIONS
Systems and methods are disclosed herein relating to fusion reactors for fusing particles via multiple periodic collisions. A fusion reactor may include a...
2017/0309350 Data Storage Device and Data Maintenance Method Thereof
An exemplary embodiment provides a data storage device including a flash memory and a controller. The flash memory includes a plurality of chips, each of the...
2017/0309349 FAILURE ANALYSIS AND REPAIR REGISTER SHARING FOR MEMORY BIST
A built-in self-test (BIST) system comprising repair logic structured to share state logic of failed memories across local registers located in a shared...
2017/0309348 CONTINUOUS WRITE AND READ OPERATIONS FOR MEMORIES WITH LATENCIES
A method and apparatus for continuous write and read operations during memory testing. The method comprises: controlling a signal generator; triggering a write...
2017/0309347 STATE MACHINE CONTROLLED MOS LINEAR RESISTOR
A sample-and-hold circuit includes a sampling capacitor, a first transistor, a first switch between a gate electrode and a source electrode of the first...
2017/0309346 CALIBRATION APPARATUS AND METHOD FOR SAMPLER WITH ADJUSTABLE HIGH FREQUENCY GAIN
Methods and systems are described for receiving a sampling signal, pre-charging a pair of output nodes prior to a sampling interval, initiating the sampling...
2017/0309345 SHIFT REGISTER, SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE
The invention provides a semiconductor device and a shift register, in which low noise is caused in a non-selection period and a transistor is not always on....
2017/0309344 MULTI-DIE PROGRAMMING WITH DIE-JUMPING INDUCED PERIODIC DELAYS
Systems and methods for improving the reliability of data stored in memory cells are described. To mitigate the effects of trapped electrons after one or more...
2017/0309343 DATA STORAGE DEVICE AND OPERATING METHOD THEREOF
A data storage device includes a nonvolatile memory device and a controller configured to control an operation of the nonvolatile memory device. The controller...
2017/0309342 NON-VOLATILE SEMICONDUCTOR MEMORY HAVING MULTIPLE EXTERNAL POWER SUPPLIES
A memory device includes core memory such as flash memory for storing data. The memory device includes a first power input to receive a first voltage used to...
2017/0309341 METHODS OF OPERATING A MEMORY DEVICE COMPARING INPUT DATA TO DATA STORED IN MEMORY CELLS COUPLED TO A DATA LINE
Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level...
2017/0309340 Independent Multi-Plane Read And Low Latency Hybrid Read
Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading...
2017/0309339 ARCHITECTURE FOR CMOS UNDER ARRAY
Systems and methods for reducing the area and improving the performance of a non-volatile memory array are described. The non-volatile memory array may...
2017/0309338 INDEPENDENT MULTI-PLANE READ AND LOW LATENCY HYBRID READ
Read operations are performed in a multi-plane memory device. A state machine interfaces an external controller to each plane of memory cells to allow reading...
2017/0309337 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second...
2017/0309336 SEMICONDUCTOR STORAGE DEVICE
A semiconductor storage device including a plurality of memory cells, each including a variable resistance element, and control circuitry that executes a first...
2017/0309335 NON-VOLATILE MEMORY DEVICE AND METHOD OF CONTROLLING NON-VOLATILE MEMORY DEVICE
A non-volatile memory device of the disclosure includes a memory cell, a writing circuit, and a current controller. The memory cell is disposed at an...
2017/0309334 METHODS FOR ENHANCED STATE RETENTION WITHIN A RESISTIVE CHANGE CELL
A method for improving the stability of a resistive change cell is disclosed. The stability of a resistive change memory cell-that is, the tendency of the...
2017/0309333 OPERATIONAL SIGNALS GENERATED FROM CAPACITIVE STORED CHARGE
Methods, a memory device, and a system. are disclosed. One such method includes applying a select pulse to a snapback device of a memory cell. This causes the...
2017/0309332 PLANAR MEMORY CELL ARCHITECTURES IN RESISTIVE MEMORY DEVICES
To provide enhanced data storage devices and systems, various systems, architectures, apparatuses, and methods, are provided herein. In a first example, a...
2017/0309331 APPARATUSES AND METHODS OF READING MEMORY CELLS BASED ON RESPONSE TO A TEST PULSE
The disclosed technology generally relates to memory apparatuses and methods of operating the same, and more particularly to memory arrays and methods of...
2017/0309330 RESISTIVE MEMORY DEVICE AND A MEMORY SYSTEM INCLUDING THE SAME
A memory device includes a memory cell array, a read circuit, and a control logic. The memory cell array includes a memory cell having a resistance level that...
2017/0309329 Non-Volatile Semiconductor Memory Device Adapted to Store a Multi-Valued Data in a Single Memory Cell
A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data...
2017/0309328 LOCAL BIT LINE-SHARING MEMORY DEVICE AND METHOD OF DRIVING THE SAME
Disclosed is a local bit line-sharing memory device, including a plurality of memory cells that share a local bit line pair; a pre-charging unit that is...
2017/0309327 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SYSTEM
A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated...
2017/0309326 SEMICONDUCTOR DEVICE
A semiconductor device includes a SRAM circuit. The SRAM circuit includes: a memory array having a plurality of memory cells arranged in a matrix; a ground...
2017/0309325 SEMICONDUCTOR DEVICE, CIRCUIT BOARD, AND ELECTRONIC DEVICE
A semiconductor device with low power consumption or a semiconductor device with a reduced area is provided. The semiconductor device includes a cell array...
2017/0309324 VOLATILE MEMORY DEVICE EMPLOYING A RESISTIVE MEMORY ELEMENT
A volatile resistive memory device includes a resistive memory element including a barrier material portion and a charge-modulated resistive memory material...
2017/0309323 METHODS AND APPARATUSES INCLUDING COMMAND DELAY ADJUSTMENT CIRCUIT
Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that...
2017/0309322 Memory Arrays, Ferroelectric Transistors, and Methods of Reading and Writing Relative to Memory Cells of Memory...
Some embodiments include a ferroelectric transistor. The transistor has gate dielectric material configured as a first container, with the first container...
2017/0309321 Peak Current Bypass Protection Control Device Applicable in MRAM
A peak current bypass protection control device applicable in MRAM is provided. In a memory unit array formed of a plurality of magnetic memory bit cells, each...
2017/0309320 METHODS AND APPARATUSES INCLUDING COMMAND DELAY ADJUSTMENT CIRCUIT
Apparatuses for controlling latencies on input signal paths in semiconductor devices are disclosed. An example apparatus includes: a clock input buffer that...
2017/0309319 APPARATUSES AND METHODS FOR DETECTING FREQUENCY RANGES CORRESPONDING TO SIGNAL DELAYS OF CONDUCTIVE VIAS
Apparatuses for monitoring a signal on a conductive via are described. An example apparatus includes: a controller, a first conductive via, a second conductive...
2017/0309318 APPARATUSES AND METHODS FOR MEMORY OPERATIONS HAVING VARIABLE LATENCIES
Apparatuses and methods for performing memory operations are described. In an example apparatus, a memory is configured to receive a memory instruction and...
2017/0309317 RECEPTION CIRCUIT AND ELECTRONIC APPARATUS INCLUDING THE SAME
Provided is a reception circuit provided in a chip, the reception circuit including a controller that generates a reception control signal which is activated...
2017/0309316 APPARATUSES AND METHODS FOR PERFORMING CORNER TURN OPERATIONS USING SENSING CIRCUITRY
The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a...
2017/0309315 SIMULATING ACCESS LINES
Examples of the present disclosure provide apparatuses and methods for simulating access lines in a memory. An example method can include receiving a first...
2017/0309314 APPARATUSES AND METHODS FOR PERFORMING CORNER TURN OPERATIONS USING SENSING CIRCUITRY
The present disclosure includes apparatuses and methods related to performing corner turn operations using sensing circuitry. An example apparatus comprises a...
2017/0309313 SEMICONDUCTOR DEVICE
According to an embodiment, a semiconductor device includes a substrate, a connector, a volatile semiconductor memory element, multiple nonvolatile...
2017/0309312 METHODS AND DEVICES FOR DETECTING SHOCK EVENTS
An apparatus includes an actuator assembly, a dampening assembly coupled to the actuator assembly, and a vibration sensor assembly coupled to the dampening...
2017/0309311 GENERATING VIDEOS OF MEDIA ITEMS ASSOCIATED WITH A USER
A method includes grouping media items associated with a user into segments based on a timestamp associated with each media item and a total number of media...
2017/0309310 METHOD AND DEVICE FOR COMPRESSED-DOMAIN VIDEO EDITING
A method and device for editing a media file comprising input video frames. The editing device comprises a frame analyzer to determine whether the input video...
2017/0309309 SYSTEM, APPARATUS AND METHOD FOR FORMATTING A MANUSCRIPT AUTOMATICALLY
System, method and apparatuses of the present invention directed to a paradigm of manuscript generation and manipulation from a source textual document,...
2017/0309308 DISPLAY APPARATUS AND CONTROL METHOD THEREOF
A display apparatus including a display unit, adapted to playback a sequence of images, comprises: a detection configured to detect an attitude of the display...
2017/0309307 VIDEO RECORDING APPARATUS WITH PRE-EVENT CIRCULATION RECORDING FUNCTION
A video recording apparatus with a pre-event circulation recording function is provided. A limitation on memory capacity may be removed by recording a...
2017/0309306 DEVICE FOR AND METHOD OF ENABLING THE PROCESSING OF A VIDEO STREAM
A method of enabling processing of a video stream is described. The method comprises establishing a slice width for frames of the video stream; receiving the...
2017/0309305 SKIVING BLOCK FOR MITIGATING PROTRUDING DEFECTS FROM MAGNETIC TAPE RECORDING MEDIA
An apparatus according to one embodiment includes a block having multiple skiving edges along a tape bearing surface thereof, and a guide mechanism configured...
2017/0309304 HARDWARE BASED CROSSTALK REDUCTION FOR HARD DISK DRIVES
An actuator assembly for crosstalk reduction in hard disk drives (HDDs) is provided. The actuator assembly comprises a base plate; a pivot; a voice coil motor...
2017/0309303 SUSPENSION ASSEMBLY WITH LIFT TAB, DISK DRIVE WITH THE SAME, AND METHOD OF MANUFACTURING LIFT TAB OF SUSPENSION...
According to one embodiment, a suspension assembly includes a support plate and a lift tab extending in a first direction. The lift tab has an arc-shaped cross...
2017/0309302 CURRENT PERPENDICULAR-TO-PLANE SENSORS HAVING HARD SPACERS
An apparatus according to one embodiment includes a transducer structure having a lower shield and/or an upper shield. A current-perpendicular-to-plane sensor...
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