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| Patent # | Description |
|---|---|
| 2017/0317103 |
INTEGRATED CIRCUITS WITH SELECTIVELY STRAINED DEVICE REGIONS AND METHODS
FOR FABRICATING SAME Integrated circuits and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing... |
| 2017/0317102 |
Flexible Single-Crystalline Semiconductor Device and Fabrication Methods
Thereof Systems and methods herein relate to the fabrication of a single-crystal flexible semiconductor template that may be attached to a semiconductor device. The... |
| 2017/0317101 |
SEMICONDUCTOR DEVICE A well potential supply region is provided in an N-type well region of a cell array. Adjacent gates disposed in both sides of the well potential supply region... |
| 2017/0317100 |
INTEGRATED CIRCUIT INCLUDING COMPLEX LOGIC CELL An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input... |
| 2017/0317099 |
Integrated Structures Comprising Vertical Channel Material and Having
Conductively-Doped Semiconductor Material... Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower... |
| 2017/0317098 |
Integrated Structures Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and ... |
| 2017/0317097 |
METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE AND SEMICONDUCTOR
DEVICE STRUCTURE A semiconductor device structure includes a hybrid substrate having a semiconductor-on-insulator (SOI) region that includes an active semiconductor layer, a... |
| 2017/0317096 |
THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE A three-dimensional semiconductor memory device includes stacked structures, vertical semiconductor patterns, common source regions, and well pickup regions.... |
| 2017/0317095 |
SPLIT GATE MEMORY DEVICES AND METHODS OF MANUFACTURING Some embodiments of the present disclosure relate to method of forming a memory device. In some embodiments, the method may be performed by forming a floating... |
| 2017/0317094 |
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE A semiconductor device having good characteristics without variation and a method of manufacturing the same are provided. A part of a conductive layer for a... |
| 2017/0317093 |
Split-Gate, Twin-Bit Non-volatile Memory Cell A memory device that includes a substrate of semiconductor material of a first conductivity type, first and second regions spaced apart in the substrate and... |
| 2017/0317092 |
STRUCTURE OF MEMORY CELL WITH ASYMMETRIC CELL STRUCTURE AND METHOD FOR
FABRICATING THE SAME A memory cell disposed on a substrate has a first gate structure and a second gate structure. The memory cell includes a first heavily doped region adjacent to... |
| 2017/0317091 |
STATIC RANDOM-ACCESS MEMORY (SRAM) CELL ARRAY A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein... |
| 2017/0317090 |
METHOD OF FORMING STATIC RANDOM-ACCESS MEMORY (SRAM) CELL ARRAY A static random-access memory (SRAM) cell array forming method includes the following steps. A plurality of fin structures are formed on a substrate, wherein... |
| 2017/0317089 |
METHOD OF MANUFACTURING FINS AND SEMICONDUCTOR DEVICE WHICH INCLUDES FINS A method, of manufacturing fins for a semiconductor device which includes Fin-FETs, includes: forming a structure including a semiconductor substrate and... |
| 2017/0317088 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and an opening. The pad structure may include a... |
| 2017/0317087 |
STATIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME A Static Random Access Memory (SRAM) cell includes a first pull-up transistor and a first pull-down transistor, a second pull-up transistor and a second... |
| 2017/0317086 |
Method of Forming Conductive Material of a Buried Transistor Gate Line and
Method of Forming a Buried... A method of forming conductive material of a buried transistor gate line includes adhering a precursor comprising tungsten and chlorine to material within a... |
| 2017/0317085 |
SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND AUTHENTICATION SYSTEM A novel semiconductor device is provided. A memory cell MC has a function of supplying a signal corresponding to the product of first data and second data to a... |
| 2017/0317084 |
INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING THE SAME An integrated circuit device as provided herein may include a device region and an inter-device isolation region. Within the device region, a fin-type active... |
| 2017/0317083 |
SEMICONDUCTOR DEVICE HAVING HETEROGENEOUS STRUCTURE AND METHOD OF FORMING
THE SAME A semiconductor device is provided as follows. A first buffer layer is disposed on a substrate including NMOS and PMOS regions. A first drain and a first... |
| 2017/0317082 |
FIELD EFFECT TRANSISTOR STRUCTURE FOR REDUCING CONTACT RESISTANCE A circuit component comprises a row of transistors. The row may contain a first active FET with a source region and a drain region. The row may also contain a... |
| 2017/0317081 |
SEMICONDUCTOR DEVICES HAVING BRIDGE LAYER AND METHODS OF MANUFACTURING THE
SAME A semiconductor device includes a substrate, a first active fin and a second active fin on the substrate, respectively, a plurality of first epitaxial layers... |
| 2017/0317080 |
INTEGRATION OF VERTICAL TRANSISTORS WITH 3D LONG CHANNEL TRANSISTORS A method for integrating a vertical transistor and a three-dimensional channel transistor includes forming narrow fins and wide fins in a substrate; forming a... |
| 2017/0317079 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME A semiconductor device includes a substrate having an active pattern, a conductive pattern crossing the active pattern, a spacer structure on at least one side... |
| 2017/0317078 |
SOURCE/DRAIN REGIONS IN FIN FIELD EFFECT TRANSISTORS (FINFETS) AND METHODS
OF FORMING SAME An embodiment method includes forming first dummy gate stack and a second dummy gate stack over a semiconductor fin. A portion of the semiconductor fin is... |
| 2017/0317077 |
SEMICONDUCTOR DEVICE WITH DIFFERENT FIN PITCHES A method for forming a semiconductor device includes forming a first fin and a second fin on a substrate, the first fin arranged in parallel with the second... |
| 2017/0317076 |
SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME In a method of manufacturing a semiconductor device, first and second gate structures are formed. The first (second) gate structure includes a first (second)... |
| 2017/0317075 |
DIODE AND POWER CONVERTOR USING THE SAME A diode includes an anode electrode layer; a cathode electrode layer; a buffer layer of a first conductivity type formed between the anode electrode layer and... |
| 2017/0317074 |
SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a first gate structure on a first side of an... |
| 2017/0317073 |
FinFET Varactor with Low Threshold Voltage and Method of Making the Same Disclosed is a FinFET varactor with low threshold voltage and methods of making the same. A disclosed method includes receiving a semiconductor layer over a... |
| 2017/0317072 |
METHOD OF FORMING A HETEROJUNCTION SEMICONDUCTOR DEVICE HAVING INTEGRATED
CLAMPING DEVICE A cascode switch structure includes a group III-V transistor structure having a first current carrying electrode, a second current carrying electrode and a... |
| 2017/0317071 |
FIN DIODE WITH INCREASED JUNCTION AREA A method incudes forming a first plurality of fins having a first width in a first region of a semiconductor substrate. A second plurality of fins having a... |
| 2017/0317070 |
APPARATUSES FOR COMMUNICATION SYSTEMS TRANSCEIVER INTERFACES An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a semiconductor... |
| 2017/0317069 |
ESD PROTECTION DEVICE The present invention is provided with a Si substrate, an ESD protection circuit formed in the Si substrate, pads formed on the surface of the Si substrate and... |
| 2017/0317068 |
SEMICONDUCTOR DEVICE A semiconductor device includes a semiconductor substrate, an element region including an active element formed at the semiconductor substrate, a channel... |
| 2017/0317067 |
Optoelectronic Semiconductor Device and Apparatus with an Optoelectronic
Semiconductor Device An optoelectronic semiconductor device and an apparatus with an optoelectronic semiconductor device are disclosed. In an embodiment the optoelectronic... |
| 2017/0317066 |
SEMICONDUCTOR DEVICE Provided is a semiconductor device with a reduced variation in temperature among a plurality of unit transistors. A semiconductor device includes: a... |
| 2017/0317065 |
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE The present disclosure allows for reducing parasitic capacitance of a bit line, and a drop in access performance in an SRAM cell including fin-type ... |
| 2017/0317064 |
Oversized Contacts and Vias in Layout Defined by Linearly Constrained
Topology A rectangular-shaped interlevel connection layout structure is defined to electrically connect a first layout structure in a first chip level with a second... |
| 2017/0317063 |
INTEGRATED CIRCUIT, SYSTEM FOR AND METHOD OF FORMING AN INTEGRATED CIRCUIT A method of forming an integrated circuit is disclosed. The method includes generating, by a processor, a layout design of the integrated circuit, outputting... |
| 2017/0317062 |
METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE A method of fabricating a semiconductor package includes providing a lower semiconductor package including a lower package substrate, and a lower dummy ball... |
| 2017/0317061 |
SEMICONDUCTOR APPARATUS, PRODUCTION METHOD, AND ELECTRONIC APPARATUS The present technology relates to a semiconductor apparatus, a production method, and an electronic apparatus that enable semiconductor apparatuses to be... |
| 2017/0317060 |
SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD A semiconductor device includes: one or more semiconductor dice, a die pad supporting the semiconductor die or dice, a package molded onto the semiconductor... |
| 2017/0317059 |
ELECTRONIC DEVICE WITH ELECTRONIC CHIPS AND HEAT SINK An electronic device includes a first support platelet and a second support platelet that is disposed opposite and at a distance from the first support... |
| 2017/0317058 |
CHIP PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip package stacked over the... |
| 2017/0317057 |
PACKAGE-ON-PACKAGE DEVICE WITH SUPPLEMENTAL UNDERFILL AND METHOD FOR
MANUFACTURING THE SAME A method of forming a semiconductor device includes the following operations: (i) receiving a precursor package including a precursor substrate and a plurality... |
| 2017/0317056 |
SEMICONDUCTOR CHIP AND STACKED SEMICONDUCTOR CHIP USING THE SAME The present disclosure provides a semiconductor chip including a semiconductor substrate having a front surface and a rear surface which faces away from the... |
| 2017/0317055 |
INTEGRATED WAFER-LEVEL PROCESSING SYSTEM Examples of techniques for an integrated wafer-level processing system are disclosed. In one example implementation according to aspects of the present... |
| 2017/0317054 |
PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME A package structure includes a molding material, at least one through-via, at least one conductor, at least one dummy structure and an underfill. The... |
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