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Patent # Description
2017/0317053 Three-Layer Package-on-Package Structure and Method Forming Same
A method includes forming a first plurality of redistribution lines, forming a first metal post over and electrically connected to the first plurality of...
2017/0317052 Wafer Bonding Edge Protection Using Double Patterning With Edge Exposure
Wafer bonding edge protection techniques are provided. In one aspect, a method of forming Cu interconnects in a wafer includes: forming a dielectric layer on...
2017/0317051 METHOD FOR COHESIVELY CONNECTING A FIRST COMPONENT OF A POWER SEMICONDUCTOR MODULE TO A SECOND COMPONENT OF A...
A method for cohesively connecting a first component of a power semiconductor module to a second component of a power semiconductor module by sintering, the...
2017/0317050 SOLID-STATE WAFER BONDING OF FUNCTIONAL MATERIALS ON SUBSTRATES AND SELF-ALIGNED CONTACTS
A method for integrating III-V semiconductor materials onto a rigid host substrate deposits a thin layer of reactive metal film on the rigid host substrate....
2017/0317049 POWER SEMICONDUCTOR CONTACT STRUCTURE AND METHOD FOR THE PRODUCTION THEREOF
A power semiconductor contact structure for power semiconductor modules, which has at least one substrate 1 and a metal moulded body 2 as an electrode, which...
2017/0317048 CONDUCTIVE BONDED ASSEMBLY OF ELECTRONIC COMPONENT, SEMICONDUCTOR DEVICE USING SAME, AND METHOD OF PRODUCTION...
The present invention provides a conductive bonded assembly utilizing particles of Ni or an Ni alloy as conductive particles so as to enable firing under...
2017/0317046 NANOMICROCRYSTALLITE PASTE FOR PRESSURELESS SINTERING
A sintering paste includes solvent and nanomicrocrystallite (NMC) particles. Each NMC particle is a single crystallite having at least one dimension in the...
2017/0317045 MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE
A manufacturing method of a semiconductor package includes locating, on a substrate, a semiconductor device having an external terminal provided on a top...
2017/0317044 Solder Bump for Ball Grid Array
A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM...
2017/0317043 METHOD FOR WAFER DICING
The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding...
2017/0317042 Multi-Layer Metal Pads
A method for fabricating a semiconductor device includes forming a conductive liner over a first landing pad in a first region and over a second landing pad in...
2017/0317041 STACKABLE SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF
A stackable semiconductor package and manufacturing method thereof are provided. The stackable semiconductor package includes carrier, first RDL, encapsulation...
2017/0317040 SUBSTRATE STRUCTURE
Provided is a substrate structure, including: a substrate body having a conductive contact; an insulating layer formed on the substrate body with the...
2017/0317039 BONDING PAD STRUCTURE OVER ACTIVE CIRCUITRY
Various embodiments provide a bonding pad structure that is capable of handling increased bonding loads. In one embodiment, the bonding pad structure includes...
2017/0317038 PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a first shielding feature over a...
2017/0317037 METHOD FOR MANUFACTURING A SEAL RING STRUCTURE TO AVOID DELAMINATION DEFECT
A method for manufacturing a semiconductor device includes providing a semiconductor substrate, forming a plurality of integrated circuit (IC) devices on the...
2017/0317036 Cavity based feature on chip carrier
A package comprising an electronic chip with at least one electric contact structure, an electrically conductive chip carrier having at least one coupling...
2017/0317035 SEMICONDUCTOR DEVICE, SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE
Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the...
2017/0317034 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A method of manufacturing a semiconductor device includes: receiving a semiconductor structure having a chip region, a seal ring region surrounding the chip...
2017/0317033 SEMICONDUCTOR MANUFACTURING PROCESS AND PACKAGE CARRIER
A package carrier includes a carrier and a light absorption layer. The light absorption layer is disposed on the carrier. The light absorption layer includes a...
2017/0317032 COMPOSITE MANGANESE NITRIDE / LOW-K DIELECTRIC CAP
A semiconductor device includes a metal-containing structure such as a copper-containing wire or plug and a composite capping layer formed over the...
2017/0317031 Fabrication Method OF A Package Substrate
This disclosure provides a package substrate and its fabrication method. The package substrate comprises: a first wiring layer including at least one first...
2017/0317030 Structure and Formation Method for Chip Package
Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely...
2017/0317029 DUMMY FEATURES IN REDISTRIBUTION LAYERS (RDLS) AND METHODS OF FORMING SAME
An embodiment device includes an integrated circuit die and a first metallization pattern over the integrated circuit die. The first metallization pattern...
2017/0317028 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES
Semiconductor devices and methods of manufacturing semiconductor devices. One example of a method of fabricating a semiconductor device comprises forming a...
2017/0317027 POWER STRAP STRUCTURE FOR HIGH PERFORMANCE AND LOW CURRENT DENSITY
The present disclosure relates to an integrated chip that uses a metal strap to improve performance and reduce electromigration by coupling a ...
2017/0317026 SELECTIVE AND NON-SELECTIVE BARRIER LAYER WET REMOVAL
A method for manufacturing a semiconductor device includes forming a dielectric layer on a substrate, forming a plurality of openings in the dielectric layer,...
2017/0317025 STRUCTURE AND METHOD FOR MAXIMIZING AIR GAP IN BACK END OF THE LINE INTERCONNECT THROUGH VIA LANDING MODIFICATION
A method of forming an interconnect to an electrical device is provided. The structure produced by the method may include a plurality of metal lines in a...
2017/0317024 SEMICONDUCTOR DEVICE
Characteristics of a semiconductor device are improved. A semiconductor device includes a coil CL1 and a wiring M2 formed on an interlayer insulator IL2, a...
2017/0317023 PACKAGED SEMICONDUCTOR DEVICES WITH WIRELESS CHARGING MEANS
A method for packaging a semiconductor device used in an electronic apparatus having wireless charging function is provided. The method includes coupling a...
2017/0317022 RUTHENIUM METAL FEATURE FILL FOR INTERCONNECTS
A method is provided for at least partially filling a feature in a substrate. The method includes providing a substrate containing a feature, depositing a...
2017/0317021 PACKAGED SEMICONDUCTOR DEVICES WITH MULTI-USE INPUT CONTACTS AND RELATED METHODS
A semiconductor device includes a first contact receiving a first voltage, a second contact receiving a second voltage, one or more comparing elements...
2017/0317020 APPARTUS AND METHODS FOR MULTI-DIE PACKAGING
A semiconductor device assembly incudes an interposer having an opening extending from a first major surface to a second major surface of the interposer and a...
2017/0317019 INTEGRATED INTERPOSER SOLUTIONS FOR 2D AND 3D IC PACKAGING
An integrated circuit (IC) package includes a first substrate having a backside surface and a top surface with a cavity disposed therein. The cavity has a...
2017/0317018 APPLICANT SCREENING
Systems and methods for screening applicants are disclosed herein. A method of screening applicants is performed by a screening server. The server begins by...
2017/0317017 PRINTED WIRING BOARD AND METHOD FOR MANUFACTURING THE SAME
A printed wiring board includes a support plate, and a build-up wiring layer including resin insulating layers and conductor layers and having a first surface...
2017/0317016 Package with vertical interconnect between carrier and clip
A package comprising a chip carrier, an electronic chip on the chip carrier, a clip on the electronic chip, an encapsulant at least partially encapsulating the...
2017/0317015 POWER MODULE PACKAGE HAVING PATTERNED INSULATION METAL SUBSTRATE
A packaging structure is provided, including a substrate, a first chip, a second chip, and a conductive unit. The substrate includes a metal carrier, a...
2017/0317014 POWER MODULE PACKAGE HAVING PATTERNED INSULATION METAL SUBSTRATE
A power module package is provided, including a substrate, a first chip, and a second chip. The substrate includes a metal carrier, a patterned insulation...
2017/0317013 SHUNT STRIP
A shunt strip that includes a plurality of shunts arranged in a grid with each of the shunts spaced from an adjacent shunt by a shunt-gap. A plurality of tabs...
2017/0317012 MULTI-FINGER TRANSISTOR AND SEMICONDUCTOR DEVICE
A multi-finger transistor includes a circuit suppressing a variation in voltage current distribution. The circuit connects gate fingers (21) to each other, or...
2017/0317011 Through-Substrate Vias with Improved Connections
A device includes a substrate, and a plurality of dielectric layers over the substrate. A plurality of metallization layers is formed in the plurality of...
2017/0317010 METHOD FOR FORMING INTERCONNECT STRUCTURE OF SEMICONDUCTOR DEVICE
A method for forming a semiconductor device structure is provided. The method includes forming a dielectric layer over a semiconductor substrate and forming an...
2017/0317009 HEAT DISSIPATION SUBSTRATE AND METHOD FOR PRODUCING HEAT DISSIPATION SUBSTRATE
A heat dissipation substrate having the maximum value of the coefficient of linear expansion of 10 ppm/K or less in any direction in a plane parallel to the...
2017/0317008 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME
A semiconductor device includes a heat-dissipating base, a first conductive layer bonded to the top surface of the heat-dissipating base, an AlN insulating...
2017/0317007 HEAT DISSIPATION COMPONENT AND METHOD FOR MANUFACTURING SAME
To provide a method for manufacturing a heat dissipation component having excellent heat dissipation properties, in which there is minimal return of warping...
2017/0317006 SEMICONDUCTOR DEVICE AND POWER MODULE
A semiconductor device of a double-side cooling structure having a bus bar electrically connected, and coolers independently arranged on both sides of the...
2017/0317005 Electronic Component Having a Heat-Sink Thermally Coupled to a Heat-Spreader
An electronic component includes one or more semiconductor dice embedded in a first dielectric layer, a heat-spreader embedded in a second dielectric layer and...
2017/0317004 Thermal Dissipation Through Seal Rings in 3DIC Structure
A package includes a die, which includes a semiconductor substrate, a plurality of through-vias penetrating through the semiconductor substrate, a seal ring...
2017/0317003 Thermal Management Structure with Integrated Heat Sink
A thermal management structure for a device is provided. The thermal management structure includes electroplated metal, which connects multiple contact regions...
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