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Patent # Description
2017/0323973 SOI WAFERS AND DEVICES WITH BURIED STRESSOR
A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer...
2017/0323972 FIELD EFFECT TRANSISTOR WITH NARROW BANDGAP SOURCE AND DRAIN REGIONS AND METHOD OF FABRICATION
A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer...
2017/0323971 FINFET DEVICE
A FinFET device and a method of forming the same are disclosed. In accordance with some embodiments, a FinFET device includes a substrate having at least one...
2017/0323970 DEVICES AND METHODS FOR A POWER TRANSISTOR HAVING A SCHOTTKY OR SCHOTTKY-LIKE CONTACT
Devices, structures, and methods thereof for providing a Schottky or Schottky-like contact as a source region and/or a drain region of a power transistor are...
2017/0323969 SGT-INCLUDING PILLAR-SHAPED SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME
A first contact hole is formed so as to extend to a NiSi layer as a lower wiring conductor layer connecting to an N+ layer of an SGT formed within a Si pillar,...
2017/0323968 PRECISE CONTROL OF VERTICAL TRANSISTOR GATE LENGTH
A transistor includes a vertical channel fin directly on a bottom source/drain region. A gate stack is formed on sidewalls of the vertical channel fin. Spacers...
2017/0323967 PRECISE CONTROL OF VERTICAL TRANSISTOR GATE LENGTH
Transistor and methods of forming the same include forming a channel fin on a bottom source/drain region. A dielectric fill is formed around the channel fin...
2017/0323966 SOURCE/DRAIN CONTACTS FOR NON-PLANAR TRANSISTORS
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description...
2017/0323965 TRIGATE TRANSISTOR STRUCTURE WITH UNRECESSED FIELD INSULATOR AND THINNER ELECTRODES OVER THE FIELD INSULATOR
Techniques related to integrated circuits having MOSFETs with an unrecessed field insulator and thinner electrodes over the field insulator of ICs, systems...
2017/0323964 SPLIT FIN FIELD EFFECT TRANSISTOR ENABLING BACK BIAS ON FIN TYPE FIELD EFFECT TRANSISTORS
A method of forming the semiconductor device that may include forming a trench in a substrate, and forming a metal nitride in the trench. The method may...
2017/0323963 THIN CHANNEL REGION ON WIDE SUBFIN
An embodiment includes a device comprising: a fin structure including an upper portion and a lower portion, the upper portion having a bottom surface directly...
2017/0323962 CARRIER CONFINEMENT FOR HIGH MOBILITY CHANNEL DEVICES
An embodiment includes a device comprising: a trench that includes a doped trench material having: (a)(i) a first bulk lattice constant and (a)(ii) at least...
2017/0323961 SEMICONDUCTOR DEVICE COMPRISING A GATE FORMED FROM A GATE RING
In some examples, a semiconductor device includes a substrate, a first doped region formed in the substrate, a second doped region around and spaced apart from...
2017/0323960 EPITAXIAL WAFER, SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING EPITAXIAL WAFER, AND METHOD FOR PRODUCING...
An epitaxial wafer including: a silicon-based substrate; a first buffer layer on the substrate and including a first multilayer structure buffer region...
2017/0323959 INSULATED GATE POWER SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SUCH A DEVICE
An insulated gate power semiconductor device has an (n-) doped drift layer between an emitter side and a collector side. A trench gate electrode has a trench...
2017/0323958 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
In one embodiment, an IGBT is formed to include a region of semiconductor material. Insulated gate structures are disposed in region of semiconductor material...
2017/0323957 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for...
2017/0323956 PUNCH THROUGH STOPPER IN BULK FINFET DEVICE
A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting...
2017/0323955 APPARATUS AND METHODS OF FORMING FIN STRUCTURES WITH SIDEWALL LINER
An includes an epitaxial sub-fin structure disposed on a substrate, wherein a first portion of the sub-fin structure is disposed within a portion of the...
2017/0323954 FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE AND MANUFACTURING METHOD THEREOF
A fin-type field effect transistor including a substrate, insulators, a gate stack, a seal spacer, a first offset spacer, and a second offset spacer is...
2017/0323953 Integrated strained stacked nanosheet FET
Transistors and methods of forming the same include forming a fin of alternating layers of a channel material and a sacrificial material. Stress liners are...
2017/0323952 Integrated strained stacked nanosheet FET
Transistors include multiple stress liners. One or more channel structures are suspended at opposite ends from the plurality of stress liners. The stress...
2017/0323951 DUMMY GATE FORMATION USING SPACER PULL DOWN HARDMASK
Forming a dummy gate on a semiconductor device is disclosed. A first sacrificial layer is formed on a fin, and a second sacrificial layer is formed on the...
2017/0323950 SEMICONDUCTOR PROCESS
A semiconductor process is described. A silicon-phosphorus (SiP) epitaxial layer is formed serving as a source/drain (S/D) region. A crystalline metal silicide...
2017/0323949 PROTECTION OF HIGH-K DIELECTRIC DURING RELIABILITY ANNEAL ON NANOSHEET STRUCTURES
A starting structure for forming a gate-all-around field effect transistor (FET) and a method of fabricating the gate-all-around FET. The method includes...
2017/0323948 VERTICAL TRANSISTOR WITH A BODY CONTACT FOR BACK-BIASING
A method of forming a substrate contact in a vertical transistor device includes patterning a sacrificial layer to form an opening in the sacrificial layer,...
2017/0323947 SCHOTTKY DEVICE AND METHOD OF MANUFACTURE
A Schottky device includes a plurality of mesa structures where one or more of the mesa structures includes a doped region having a multi-concentration dopant...
2017/0323946 GROUP III-N TRANSISTOR ON NANOSCALE TEMPLATE STRUCTURES
A III-N semiconductor channel is formed on a III-N transition layer formed on a (111) or (110) surface of a silicon template structure, such as a fin sidewall....
2017/0323945 A MULTILAYER GRAPHENE COMPOSITE
A multilayer graphene composite comprising a plurality of stacked graphene layers separated from one another by an ion gel, wherein the ion gel is intercalated...
2017/0323944 SPLIT FIN FIELD EFFECT TRANSISTOR ENABLING BACK BIAS ON FIN TYPE FIELD EFFECT TRANSISTORS
A method of forming the semiconductor device that may include forming a trench in a substrate, and forming a metal nitride in the trench. The method may...
2017/0323943 Integrated Circuit Structure and Method with Solid Phase Diffusion
The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and...
2017/0323942 FINFET DEVICE STRUCTURE AND METHOD FOR FORMING SAME
A low electrical and thermal resistance FinFET device includes a semiconductor body, a fin body on the substrate wafer, an isolation structure forming a fin...
2017/0323941 HORIZONTAL NANOSHEET FETS AND METHODS OF MANUFACTURING THE SAME
A horizontal nanosheet field effect transistor (hNS FET) including source and drain electrodes, a gate electrode between the source and drain electrodes, a...
2017/0323940 Block Layer in the Metal Gate of MOS Devices
A method includes method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer,...
2017/0323939 Semiconductor Film with Adhesion Layer and Method for Forming the Same
Presented herein is a device including an insulator layer disposed over a substrate. An adhesion layer is disposed over the insulator layer and includes a...
2017/0323938 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A semiconductor device is provided. The semiconductor device includes a substrate; an epitaxial layer; a first conductive type first well region disposed in...
2017/0323937 HIGH DENSITY CAPACITOR STRUCTURE AND METHOD
High density capacitor structures based on an array of semiconductor nanorods are provided. The high density capacitor structure can be a plurality of...
2017/0323935 DISPLAY DEVICE
A display device includes a first substrate arranged with a plurality of pixels on a first surface, the plurality of pixels having a display element including...
2017/0323934 Flexible Display Device with Divided Power Lines and Manufacturing Method for the Same
There is provided a flexible display having a plurality of innovations configured to allow bending of a portion or portions to reduce apparent border size...
2017/0323933 PIXEL CIRCUIT
A pixel circuit is provided comprising the following. The first transistor includes a gate electrode and a semiconductor layer comprising a channel region, a...
2017/0323932 SOLID-STATE IMAGE PICKUP DEVICE AND MANUFACTURING METHOD THEREOF
There is provided a solid-state image pickup device that includes a functional region provided with an organic film, and a guard ring surrounding the...
2017/0323931 THREE DIMENSIONAL COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CARBON NANOTUBE THIN FILM TRANSISTOR CIRCUIT
A metal oxide semiconductor carbon nanotube thin film transistor circuit includes a p-type carbon nanotube thin film transistor and a n-type carbon nanotube...
2017/0323930 METHOD FOR MAKING THREE DIMENSIONAL COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CARBON NANOTUBE THIN FILM...
A method for making a metal oxide semiconductor carbon nanotube thin film transistor circuit. A p-type carbon nanotube thin film transistor and a n-type carbon...
2017/0323929 Memory Apparatus and Method of Production Thereof
In accordance with an example embodiment of the present invention, an apparatus is disclosed. The apparatus includes a resistive memory component including an...
2017/0323928 WRITE CURRENT REDUCTION IN SPIN TRANSFER TORQUE MEMORY DEVICES
The present disclosure relates to the fabrication of spin transfer torque memory elements for non-volatile microelectronic memory devices. The spin transfer...
2017/0323927 MAGNETIC DEVICES WITH MAGNETIC AND GETTER REGIONS AND METHODS OF FORMATION
A magnetic cell includes magnetic, secondary oxide, and getter seed regions. During formation, a diffusive species is transferred from a precursor magnetic...
2017/0323926 INTERFACE SUBSTRATE AND METHOD OF MAKING THE SAME
A package may include a substrate and a semiconductor die with the substrate having a smaller width than the semiconductor die and encapsulated in a mold...
2017/0323925 MONOLITHIC MULTICOLOR DIRECT VIEW DISPLAY CONTAINING DIFFERENT COLOR LEDS AND METHOD OF MAKING THEREOF
A direct view multicolor light emitting device includes blue, green and red light emitting diodes (LEDs) in each pixel. The different light emitting diodes can...
2017/0323924 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
A semiconductor device includes a first semiconductor layer of a first conductivity type having a primary surface on one side thereof and a secondary surface...
2017/0323923 PHOTON COUNTING DEVICES
Described herein are semiconductor materials suitable for direct conversion of ionizing radiation to electron hole pairs. The material described herein have...
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