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Patent # Description
2017/0345946 SEMICONDUCTOR DEVICE
A semiconductor device according to example embodiments of inventive concepts may include a substrate, source/drain regions extending perpendicular to an upper...
2017/0345945 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a drain, a source, a gate electrode, and a nanowire between the source and drain. The nanowire has a first section with a first...
2017/0345944 Semiconductor Device with Transition Metal Dichalocogenide Hetero-Structure
The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a first transition metal...
2017/0345943 Thin Film Transistor, Array Substrate, Method for Manufacturing the Same, and Display Device
Disclosed is a thin film transistor, an array substrate, a method for manufacturing the same, and a display device. The method includes: forming a source and...
2017/0345942 THIN-FILM TRANSISTOR, DISPLAY UNIT, AND ELECTRONIC APPARATUS
A thin-film transistor includes a resin substrate and a thin-film transistor layer. The resin substrate has flexibility, and has volume resistivity of equal to...
2017/0345941 NON-VOLATILE MEMORY CELL AND NON-VOLATILE MEMORY
An non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has...
2017/0345940 SEMICONDUCTOR DEVICE AND PRODUCTION METHOD THEREFOR
A semiconductor device (100A) includes: a substrate (1); a thin film transistor (101) whose active layer is an oxide semiconductor layer 5; at least one metal...
2017/0345939 FABRICATING METHOD OF FIN FIELD EFFECT TRANSISTOR
A method for fabricating a fin field effect transistor (FinFET) is provided. The method includes: patterning a substrate to form a plurality of trenches in the...
2017/0345938 BOTTOM-UP EPITAXY GROWTH ON AIR-GAP BUFFER
A fin structure for a semiconductor device, such as a FinFET structure, has first and second semiconductor layers and an air gap between the layers. The second...
2017/0345937 METHOD FOR FORMING SEMICONDUCTOR STRUCTURE
A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate including a first semiconductor material is...
2017/0345936 FINFET AND METHOD OF FABRICATION THEREOF
The present disclosure provides a fin-like field effect transistor (FinFET) device and a method of fabrication thereof. The method includes forming a fin on a...
2017/0345935 METHOD TO FORM STRAINED CHANNEL IN THIN BOX SOI STRUCTURES BY ELASTIC STRAIN RELAXATION OF THE SUBSTRATE
Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate...
2017/0345934 REPLACEMENT BODY FINFET FOR IMPROVED JUNCTION PROFILE WITH GATE SELF-ALIGNED JUNCTIONS
After forming an epitaxial semiconductor layer on portions of a semiconductor located on opposite sides of a sacrificial gate structure, dopants from the...
2017/0345933 FINFET STRUCTURE AND METHODS THEREOF
A method and structure for providing a unique structure for FinFET S/D features described a semiconductor device including a substrate having a fin extending...
2017/0345932 SACRIFICIAL NON-EPITAXIAL GATE STRESSORS
A method for fabricating a fin field effect transistor (finFET) device with a strained channel. During fabrication, after the fin is formed, a dummy gate is...
2017/0345931 METHOD OF MAKING A TRANSISTOR HAVING A SOURCE AND A DRAIN OBTAINED BY RECRYSTALLIZATION OF SEMICONDUCTOR
Method of making a transistor, comprising the following steps: make a gate and a first spacer on a first channel region of a first crystalline semiconducting...
2017/0345930 Transistor with Asymmetric Source and Drain Regions
Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is...
2017/0345929 I-SHAPED GATE ELECTRODE FOR IMPROVED SUB-THRESHOLD MOSFET PERFORMANCE
Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are...
2017/0345928 SEMICONDUCTOR DEVICE WITH CONTAMINATION IMPROVEMENT
A semiconductor device includes a substrate, two gate structures, an interlayer dielectric layer and a material layer. The substrate has at least two device...
2017/0345927 Integrated Circuit Devices and Methods of Manufacturing the Same
An integrated circuit device may include a substrate including a main surface, a compound semiconductor nanowire extending from the main surface in a first...
2017/0345926 HIGH-VOLTAGE METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND FABRICATION METHOD THEREOF
A high-voltage MOS transistor includes a semiconductor substrate, a gate oxide layer on the semiconductor substrate, a gate on the gate oxide layer, a spacer...
2017/0345925 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
A semiconductor device includes a field effect transistor (LDMOSFET) having a field relaxing part. This field relaxing part has a trench, a charge capture...
2017/0345924 Reduced Gate Charge Field-Effect Transistor
In one implementation, a reduced gate charge field-effect transistor (FET) includes a drift region situated over a drain, a body situated over the drift...
2017/0345923 FINFET WITH P/N STACKED FINS AND METHOD FOR FABRICATING THE SAME
A semiconductor device is provided and includes a semiconductor fin protruding from a semiconductor substrate. The semiconductor fin includes plural pairs of...
2017/0345922 DOUBLE-CHANNEL HEMT DEVICE AND MANUFACTURING METHOD THEREOF
An HEMT device, comprising: a semiconductor body including a heterojunction structure; a dielectric layer on the semiconductor body; a gate electrode; a drain...
2017/0345921 POWER DEVICE AND METHOD FOR FABRICATING THEREOF
A power device having a patterned three-dimensional gate geometry is fabricated and described. The power device achieved increased effective gate width and...
2017/0345920 FIELD-EFFECT TRANSISTOR
A field-effect transistor includes: a nitride semiconductor layer that includes a heterojunction; a source electrode and a drain electrode; a first gate...
2017/0345919 SEMICONDUCTOR DEVICE
A semiconductor device includes a lateral switching device having: a substrate; a channel forming layer that has a heterojunction structure made of a GaN layer...
2017/0345918 HIGH-POWER AND HIGH-FREQUENCY HETEROSTRUCTURE FIELD-EFFECT TRANSISTOR
In an HEMT device, a gate region is formed in a wafer having a channel layer, a barrier layer, and a passivation layer, overlying each other. Drain and source...
2017/0345917 ELECTRIC ASSEMBLY INCLUDING A BIPOLAR SWITCHING DEVICE AND A WIDE BANDGAP TRANSISTOR
An electric assembly includes a bipolar switching device and a transistor circuit. The transistor circuit is electrically connected in parallel with the...
2017/0345916 SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF
A semiconductor structure and a method for fabricating a semiconductor structure are provided. The method includes forming one or more fins on a substrate,...
2017/0345915 METHOD OF PRODUCING A CHANNEL STRUCTURE FORMED FROM A PLURALITY OF STRAINED SEMICONDUCTOR BARS
Method of manufacturing a structure with semiconducting bars suitable for forming one at least one transistor channel, including the following steps: a) make...
2017/0345914 METHODS FOR FORMING INTEGRATED CIRCUITS THAT INCLUDE A DUMMY GATE STRUCTURE
A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor...
2017/0345913 METHODS FOR PERFORMING A GATE CUT LAST SCHEME FOR FINFET SEMICONDUCTOR DEVICES
A method includes forming a placeholder gate structure embedded in a dielectric layer. The placeholder gate structure includes a sacrificial material. A first...
2017/0345912 METHODS OF RECESSING A GATE STRUCTURE USING OXIDIZING TREATMENTS DURING A RECESSING ETCH PROCESS
A method includes forming a gate structure embedded in a dielectric layer above a substrate. A first recessing etch process is performed to remove a first...
2017/0345911 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a field insulating film including a first region and a second region on a substrate, a recess in the first region of the field...
2017/0345910 Platinum-Containing Constructions, and Methods of Forming Platinum-Containing Constructions
Some embodiments include constructions which have platinum-containing structures. In some embodiments, the constructions may have a planarized surface...
2017/0345909 SEMICONDUCTOR DEVICE
A semiconductor device includes a third first-conductivity-type semiconductor layer on a semiconductor substrate, and a first pillar-shaped semiconductor layer...
2017/0345908 METHOD FOR PRODUCING SEMICONDUCTOR DEVICE
A method for producing a semiconductor device includes depositing an oxide film containing an impurity having a first conductivity type on a substrate. A...
2017/0345907 THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME
Three-dimensional semiconductor memory devices and methods of fabricating the same. The three-dimensional semiconductor devices include an electrode structure...
2017/0345906 Self-Aligned Dual Trench Device
A power MOSFET or a power rectifier may be fabricated according to the invention to include a gate trench and a field plate trench. Both trenches can be formed...
2017/0345905 Wide-Bandgap Semiconductor Device with Trench Gate Structures
A semiconductor device includes trench gate structures extending from a first surface into a semiconductor body from a wide-bandgap semiconductor material. The...
2017/0345904 WRAP-AROUND CONTACT INTEGRATION SCHEME
Embodiments of the invention provide a wrap-around contact integration scheme that includes sidewall protection during contact formation. A substrate...
2017/0345903 SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE,...
A semiconductor device according to an embodiment includes a silicon carbide layer, a silicon oxide layer including carbon, the silicon oxide layer including...
2017/0345902 TRANSISTOR STRUCTURE WITH FIELD PLATE FOR REDUCING AREA THEREOF
In some embodiments, a BJT structure includes a base region, an emitter region formed in the base region and including an emitter doping region, a collector...
2017/0345901 P-TYPE OXIDE, P-TYPE OXIDE-PRODUCING COMPOSITION, METHOD FOR PRODUCING P-TYPE OXIDE, SEMICONDUCTOR DEVICE,...
A p-type oxide which is amorphous and is represented by the following compositional formula: xAO.yCu.sub.2O where x denotes a proportion by mole of AO and y...
2017/0345900 DIFFUSION TOLERANT III-V SEMICONDUCTOR HETEROSTRUCTURES AND DEVICES INCLUDING THE SAME
Semiconductor devices including a subfin including a first III-V compound semiconductor and a channel including a second III-V compound semiconductor are...
2017/0345899 SEMICONDUCTOR DEVICE
Provided is a semiconductor device according to an embodiment including an i-type or first-conductivity-type first diamond semiconductor layer having a first...
2017/0345898 GRAPHENE DOUBLE-BARRIER RESONANT TUNNELING DEVICE
An apparatus comprising: a fermion source nanolayer (90); a first insulating nanolayer (92); a fermion transport nanolayer (94); a second insulating nanolayer...
2017/0345897 VERTICAL FIELD EFFECT TRANSISTOR
A vertical field effect transistor is provided as follows. A substrate has a lower drain and a lower source arranged along a first direction in parallel to an...
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