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Patent # Description
2017/0345795 PACKAGE STRUCTURES, POP DEVICES AND METHODS OF FORMING THE SAME
Package structures, PoP devices and methods of forming the same are disclosed. A package structure includes a first chip, a redistribution layer structure, a...
2017/0345794 PACKAGE-ON-PACKAGE STRUCTURE WITH EPOXY FLUX RESIDUE
A structure includes a first package and a second package. The second package is coupled to the first package by one or more connectors. Epoxy flux residue is...
2017/0345793 SEMICONDUCTOR DEVICE
A semiconductor device includes an electronic component and a wiring structural body located below the electronic component. The wiring structural body...
2017/0345792 HALF-BRIDGE POWER SEMICONDUCTOR MODULE AND METHOD OF MANUFACTURING SAME
A half-bridge power semiconductor module includes an insulating wiring board including a positive-electrode wiring conductor, a bridge wiring conductor, and a...
2017/0345791 Integrated Circuit Structure with Active and Passive Devices in Different Tiers
An integrated circuit structure includes a two-tier die including a first tier and a second tier over and bonded to the first tier. The first tier includes a...
2017/0345790 LOCKING DUAL LEADFRAME FOR FLIP CHIP ON LEADFRAME PACKAGES
A method of assembling a flip chip on a leadframe package. A locking dual leadframe (LDLF) includes a top metal frame portion including protruding features and...
2017/0345789 Encapsulated Circuit Module, And Production Method Therefor
To provide a technique of preventing, in an encapsulated circuit module having a metal shield layer covering a surface of a resin layer containing filler, the...
2017/0345788 Warpage Control of Semiconductor Die Package
Various embodiments of mechanisms for forming a die package using a compressive dielectric layer to contact and to surround through substrate vias (TSVs) in...
2017/0345787 METHODS OF FORMING WIRE INTERCONNECT STRUCTURES
A method of forming a wire interconnect structure includes the steps of: (a) forming a wire bond at a bonding location on a substrate using a wire bonding...
2017/0345786 Structure and Method of Forming a Joint Assembly
A method of manufacturing a semiconductor device structure includes forming a bond or joint between a first device and a second device. The first device...
2017/0345785 Contact Area Design for Solder Bonding
A package component includes a dielectric layer and a metal pad over the dielectric layer. A plurality of openings is disposed in the metal pad. The first...
2017/0345784 Manufacturing Method for Electronic Element
The present invention provides a manufacturing method for an electronic element of an electronic apparatus. The electronic element includes a substrate, a bump...
2017/0345783 BUMP ON PAD (BOP) BONDING STRUCTURE IN SEMICONDUCTOR PACKAGED DEVICE
The embodiments described above provide enlarged overlapping surface areas of bonding structures between a package and a bonding substrate. By using elongated...
2017/0345782 CONNECTION STRUCTURE AND CONNECTING METHOD OF CIRCUIT MEMBER
There is provided a connection structure of a circuit member including: a first circuit member having a first main surface provided with a first electrode; a...
2017/0345781 ELEMENT CHIP MANUFACTURING METHOD
An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface having an exposed bump and a second...
2017/0345780 Surface Conditioning And Material Modification In A Semiconductor Device
A plasma-based ashing process for surface conditioning and material modification to improve bond pad metallurgical properties as well as semiconductor device...
2017/0345779 POLYMER RESIN AND COMPRESSION MOLD CHIP SCALE PACKAGE
A method for fabricating a chip scale package, comprising: providing a wafer; applying a polymer resin on at least part of a first surface of the wafer and to...
2017/0345778 HYPERFREQUENCY HOUSING OCCUPYING A SMALL SURFACE AREA AND MOUNTING OF SUCH A HOUSING ON A CIRCUIT
A package, able to encapsulate at least one component, forming a closed cavity of Faraday cage type having side walls resting on a base and that are surmounted...
2017/0345777 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A first film (3) is formed on a front surface of a semiconductor wafer (1). A second film (4) is formed on the first film (3). A surface protection film (5) is...
2017/0345775 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device with improved reliability is provided. The semiconductor device is characterized by its embodiments in that sloped portions are formed...
2017/0345774 CRACK PROPAGATION PREVENTION AND ENHANCED PARTICLE REMOVAL IN SCRIBE LINE SEALS OF SEMICONDUCTOR DEVICES
Disclosed embodiments include an integrated circuit having a semiconductor substrate with insulator layers and conductor layers overlying the semiconductor...
2017/0345773 SEMICONDUCTOR DEVICES
The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor...
2017/0345772 METHODS AND APPARATUS FOR SCRIBE STREET PROBE PADS WITH REDUCED DIE CHIPPING DURING WAFER DICING
An example apparatus includes a semiconductor wafer with a plurality of probe pads each formed centered in scribe streets and intersected by saw kerf lanes....
2017/0345771 PACKAGE SUBSTRATE WITH EMBEDDED NOISE SHIELDING WALLS
A package substrate with embedded noise shielding walls is disclosed. One of the embodiment comprises a signal line S sandwiched by a left shielding wall W1...
2017/0345770 METHOD FOR MAKING EMI SHIELDING LAYER ON A PACKAGE
A method for making EMI shielding layer of a package is disclosed to include the steps of: a) disposing a UV curable adhesive, which can be thermally released,...
2017/0345769 SEAL RING STRUCTURE AND FABRICATION METHOD THEREFOR
A method of fabricating a semiconductor structure. The method includes forming a dummy structure over a semiconductor body. The method further includes...
2017/0345768 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor substrate including a main chip region and a remaining scribe lane region surrounding the main chip region, a...
2017/0345767 MULTILAYER WIRING SUBSTRATE, DISPLAY UNIT, AND ELECTRONIC APPARATUS
In a case of a multilayer wiring structure in which an insulating layer provided between wires is made of a material having high transmittance of light in a...
2017/0345766 DEVICES AND METHODS OF FORMING LOW RESISTIVITY NOBLE METAL INTERCONNECT WITH IMPROVED ADHESION
Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects with improved adhesion are provided. One method...
2017/0345765 CONTACT STRUCTURE AND FORMATION THEREOF
A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the...
2017/0345764 INTEGRATED FAN-OUT PACKAGE AND METHOD OF FABRICATING THE SAME
A method for fabricating an integrated fan-out package is provided. The method includes the following steps. A plurality of conductive posts are placed in...
2017/0345763 FLEXIBLE PACKAGING ARCHITECTURE
A flexible packaging architecture is described that is suitable for curved package shapes. In one example a package has a first die, a first mold compound...
2017/0345762 CONDUCTIVE PATTERN AND INTEGRATED FAN-OUT PACKAGE HAVING THE SAME
A conductive pattern including a teardrop shaped portion, a routing line, and a connection portion is provided. The routing line links to the teardrop shaped...
2017/0345761 PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A package structure has a first die, a second die, the third die, a molding compound, a first redistribution layer, an antenna and conductive elements. The...
2017/0345760 SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR THE SAME
The semiconductor device includes: a transistor having a gate electrode formed on a semiconductor substrate and first and second source/drain regions formed in...
2017/0345759 A METHOD OF FORMING CONTACT TRENCH
A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack and a second gate stack over a substrate. Each of...
2017/0345758 Electrical Fuse Structure and Method of Formation
Various fuse structures are disclosed herein that exhibit improved performance, such as reduced electro-migration. An exemplary fuse structure includes an...
2017/0345757 ANTIFUSE HAVING COMB-LIKE TOP ELECTRODE
Antifuse structures are provided for use in applications such as field programmable gate arrays and programmable read-only memories. High aspect ratio channels...
2017/0345756 POWER MODULE AND POWER DEVICE
A power module and a power device having the power module are disclosed. The power device includes a main board. The power module is inserted in the main board...
2017/0345755 SEMICONDUCTOR DEVICE, ELECTRICAL ENERGY MEASUREMENT INSTRUMENT, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
According to one embodiment, a semiconductor device 1 includes an Si substrate 11, an inductor 12 formed in wiring layers disposed above the Si substrate 11,...
2017/0345754 THREE-DIMENSIONAL INDUCTOR STRUCTURE AND STACKED SEMICONDUCTOR DEVICE INCLUDING THE SAME
A three-dimensional (3D) inductor structure comprising: a first semiconductor die including: a first conductive pattern; and a second conductive pattern spaced...
2017/0345753 INTEGRATED CIRCUIT HAVING SLOT VIA AND METHOD OF FORMING THE SAME
An integrated circuit includes a first conductive line on a first metal level of the integrated circuit. The integrated circuit further includes a second...
2017/0345752 DEVICES AND METHODS OF FORMING LOW RESISTIVITY NOBLE METAL INTERCONNECT
Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance:...
2017/0345751 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes a first line pattern and a second line pattern formed in parallel on a semiconductor substrate, third line patterns formed in...
2017/0345750 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Characteristics of a semiconductor device are improved. The semiconductor device is configured to include an SOI substrate including an active region and an...
2017/0345749 POWER COMMUTATION MODULE
A power commutation module includes a printed circuit board, a first plate-shaped bus bar, and a first plurality of power switches each including a plurality...
2017/0345748 COMPOUND CARRIER BOARD STRUCTURE OF FLIP-CHIP CHIP-SCALE PACKAGE AND MANUFACTURING METHOD THEREOF
A compound carrier board structure of Flip-Chip Chip-Scale Package and manufacturing method thereof provides a baseplate with an opening bonded to a carrier...
2017/0345747 MULTILAYER SUBSTRATE AND MANUFACTURING METHOD FOR SAME
A multilayer substrate includes a component mounting substrate having component mounting and non-mounting surfaces and including connection pads on both the...
2017/0345746 INTEGRATED CIRCUIT PACKAGE WITH SOLDER BALLS ON TWO SIDES
An integrated circuit package with solder balls on two major sides of the package and a method of making. The integrated circuit package includes at least one...
2017/0345745 HIGH DENSITY SEMICONDUCTOR PACKAGE AND RELATED METHODS
Implementations of semiconductor packages may include: a first semiconductor die having a plurality of balls coupled to a first side thereof, a second...
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