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Patent # Description
2017/0352658 METHOD FOR FORMING FINFET DEVICE
A method includes providing a semiconductor structure including an active region having a first doped region, a first contact member on the first doped region,...
2017/0352657 AIR GAP SPACER FOR METAL GATES
A method of forming a semiconductor device that includes forming a trench adjacent to a gate structure to expose a contact surface of one of a source region...
2017/0352656 FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE WITH DIFFERENT GATE PROFILE AND METHOD FOR FORMING THE SAME
A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and an isolation structure formed over the...
2017/0352655 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME
A method includes forming a gate, a first dielectric layer, a first contact structure, and a second contact structure over a substrate. The first contact...
2017/0352654 METHOD OF CONCURRENTLY FORMING SOURCE/DRAIN AND GATE CONTACTS AND RELATED DEVICE
A method of concurrently forming source/drain contacts (CAs) and gate contacts (CBs) and device are provided. Embodiments include forming metal gates (PC) and...
2017/0352653 ESD PROTECTION DEVICE AND METHOD
An ESD protection device includes a substrate structure having a substrate, first and second fins, and first and second doped regions having different...
2017/0352652 OVER-VOLTAGE PROTECTION CIRCUIT
A device is disclosed that includes a first transistor, a second transistor, and a first PODE device. The second transistor is electrically coupled to the...
2017/0352651 BULK CROSS-COUPLED HIGH DENSITY POWER SUPPLY DECOUPLING CAPACITOR
In an aspect of the disclosure, a MOS device for using bulk cross-coupled thin-oxide decoupling capacitor is provided. The MOS device may include a pMOS...
2017/0352650 INTEGRATED CIRCUIT AND STANDARD CELL LIBRARY
An integrated circuit includes at least one cell. The at least one cell includes a cell region defined by a cell boundary; a power line structure extending in...
2017/0352649 METHODS AND APPARATUS FOR USING SPLIT N-WELL CELLS IN A MERGED N-WELL BLOCK
In an aspect of the disclosure, a MOS device for reducing routing congestion caused by using split n-well cells in a merged n-well circuit block is provided....
2017/0352648 Semiconductor Device, Method for Manufacturing Same, and Semiconductor Module
In order to form, in a wide band gap semiconductor device, a high field resistant sealing material having a large end portion film thickness, said high field...
2017/0352647 VOLTAGE-BALANCED SERIAL ILED PIXEL AND DISPLAY
A multi-color inorganic light-emitting diode (iLED) display includes a display substrate with a common voltage signal and a common ground signal and a...
2017/0352646 MICRO-TRANSFER-PRINTED LIGHT-EMITTING DIODE DEVICE
A compound light-emitting diode (LED) device includes a semiconductor substrate having an active electronic circuit formed in or on the semiconductor...
2017/0352645 THERMAL PADS BETWEEN STACKED SEMICONDUCTOR DIES AND ASSOCIATED SYSTEMS AND METHODS
Systems and methods are described for improved heat dissipation of the stacked semiconductor dies by including metallic thermal pads between the dies in the...
2017/0352644 APPARATUSES AND METHODS FOR SCALABLE MEMORY
Apparatuses and methods are provided for scalable memory. An example apparatus comprises a logic component, a plurality of memory components adjacent to and...
2017/0352643 DEVICES AND METHODS RELATED TO SINGULATED RADIO-FREQUENCY DEVICES
Devices and methods for processing singulated radio-frequency (RF) units. In some embodiments, a device for processing singulated RF packages can include a...
2017/0352642 APPARATUS FOR BONDING A SEMICONDUCTOR CHIP AND METHOD OF FORMING A SEMICONDUCTOR DEVICE
An apparatus for bonding a semiconductor chip to a package substrate, the apparatus comprising: a die-bonding unit configured to attach the semiconductor chip...
2017/0352641 METHOD AND SYSTEM FOR MOUNTING COMPONENTS IN SEMICONDUCTOR FABRICATION PROCESS
A method for mounting components on a substrate is provided. The method includes providing a positioning plate which has a plurality of through holes. The...
2017/0352640 REMOVAL APPARATUSES FOR SEMICONDUCTOR CHIPS AND METHODS OF REMOVING SEMICONDUCTOR CHIPS
A removal apparatus for a semiconductor chip may include a stage configured to support a board on which the semiconductor chip is mounted by bumps, a laser...
2017/0352639 METHOD FOR PROTECTING BOND PADS FROM CORROSION
Methods, systems, and apparatuses for preventing corrosion between dissimilar bonded metals. The method includes providing a wafer having a plurality of...
2017/0352638 SEMICONDUCTOR DEVICE INCLUDING ANTISTATIC DIE ATTACH MATERIAL
A semiconductor device includes a substrate, a semiconductor die, and an antistatic die attach material between the substrate and the semiconductor die. The...
2017/0352637 WAFER LAMINATE AND MAKING METHOD
A wafer laminate has an adhesive layer (2) sandwiched between a support (1) and a wafer (3), with a circuit-forming surface of the wafer facing the adhesive...
2017/0352636 ANISOTROPIC CONDUCTIVE FILM AND CONNECTION STRUCTURE
A anisotropic conductive film includes: an electrically insulating adhesive layer; electrically conductive particles disposed in lattice form in the...
2017/0352635 BONDING STRUCTURE AND METHOD
A bonding structure and a method for bonding components, wherein the bonding structure includes a nanoparticle preform. In accordance with embodiments, the...
2017/0352634 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a first die, a second die bonding to the first die thereby forming a bonding interface, and a pad of the first die and exposed...
2017/0352633 COLLARS FOR UNDER-BUMP METAL STRUCTURES AND ASSOCIATED SYSTEMS AND METHODS
The present technology is directed to manufacturing collars for under-bump metal (UBM) structures for die-to-die and/or package-to-package interconnects and...
2017/0352632 Connector Formation Methods and Packaged Semiconductor Devices
Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer...
2017/0352631 SEMICONDUCTOR DEVICE
Provided is a semiconductor device including a substrate, a pad, a protective layer, a plurality of convex patterns, a redistribution layer (RDL), and a bump....
2017/0352630 INTEGRATED CIRCUITS AND METHODS OF MANUFACTURING
A technique for making high performance low noise amplifiers, low cost high performance RF, microwave circuits and other devices by using a minimum of costly...
2017/0352629 POWER MODULE
A power module includes a power semiconductor element, an interconnection material, a circuit board, an external terminal, a joining material, and a sealing...
2017/0352628 WIRING BOARD AND SEMICONDUCTOR DEVICE
A wiring board includes a first insulating layer made of a single layer of non-photosensitive resin including a reinforcing member, a center position of the...
2017/0352627 LEAKAGE LASER BEAM DETECTING METHOD
A leakage laser beam detecting method includes a coating step of coating the lower surface of a wafer with an oil marker, thereafter, a press-bonding step of...
2017/0352625 SELF-ALIGNED VERTICAL TRANSISTOR WITH LOCAL INTERCONNECT
A metallization scheme for vertical field effect transistors (FETs) is provided. By forming lower-level local interconnects connecting source regions located...
2017/0352624 INTERCONNECT STRUCTURES WITH ENHANCED ELECTROMIGRATION RESISTANCE
Interconnect structures are provided that include an intermetallic compound as either a cap or liner material. The intermetallic compound is a thermal reaction...
2017/0352623 INTEGRATED CIRCUIT HAVING STAGGERED CONDUCTIVE FEATURES
An integrated circuit includes at least one first conductive feature and at least one second conductive feature. The second conductive feature has at least one...
2017/0352622 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
A semiconductor device according to this embodiment includes a semiconductor layer, a plurality of diffusion layers in the semiconductor layer, a gate...
2017/0352621 AVOIDING GATE METAL VIA SHORTING TO SOURCE OR DRAIN CONTACTS
Techniques relate to forming a gate metal via. A gate contact has a bottom part in a first layer. A cap layer is formed on the gate contact and first layer....
2017/0352620 Assemblies Having Shield Lines of an Upper Wiring Level Electrically Coupled with Shield Lines of a Lower...
Some embodiments include an assembly having a first wiring level with a plurality of first shield lines and first signal lines. The first shield lines and...
2017/0352619 INTERCONNECT STRUCTURE WITH CAPACITOR ELEMENT AND RELATED METHODS
Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming...
2017/0352618 INTEGRATED CIRCUIT STRUCTURE HAVING DEEP TRENCH CAPACITOR AND THROUGH-SILICON VIA AND METHOD OF FORMING SAME
One aspect of the disclosure relates to an interposer. The interposer may include: a first dielectric layer extending from a substrate in a direction away from...
2017/0352617 Methods for semiconductor component design and for semiconductor component production and corresponding...
Methods for designing semiconductor components, for fabricating semiconductor components, and corresponding semiconductor components are provided. In this...
2017/0352616 Semiconductor Constructions, Patterning Methods, and Methods of Forming Electrically Conductive Lines
Some embodiments include methods of forming electrically conductive lines. Photoresist features are formed over a substrate, with at least one of the...
2017/0352615 METHOD OF FABRICATING PACKAGE STRUCTURE WITH AN EMBEDDED ELECTRONIC COMPONENT
The present invention provides a package structure with an embedded electronic component and a method of fabricating the package structure. The method...
2017/0352614 WIRING BOARD
A wiring board includes a base board and a plurality of wiring layers formed of a resin insulating film on the base board, wherein at least one of the wiring...
2017/0352613 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
An electronic device and a method of manufacturing an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods...
2017/0352612 SEMICONDUCTOR PACKAGES INCLUDING HEAT SPREADERS AND METHODS OF MANUFACTURING THE SAME
There may be provided a method of manufacturing a semiconductor package. The method may include disposing a first semiconductor device and through mold ball...
2017/0352611 PRODUCING WAFER LEVEL PACKAGING USING LEADFRAME STRIP AND RELATED DEVICE
A method for producing wafer level packaging using an embedded leadframe strip and the resulting device are provided. Embodiments include placing dies into a...
2017/0352610 SEMICONDUCTOR PACKAGE WITH MULTIPLE MOLDING ROUTING LAYERS AND A METHOD OF MANUFACTURING THE SAME
Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing...
2017/0352609 LEAD FRAME WITH SOLDER SIDEWALLS
A leadframe wherein the outer sidewalls of the leadframe that are exposed by sawing during singulation are comprised of greater than 50% solder. A leadframe...
2017/0352608 ELECTRONIC DEVICE FOR VEHICLE
An electronic device for a vehicle includes a substrate and a semiconductor package. The substrate is arranged to extend along a flowing path of wind produced...
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