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Patent # Description
2017/0352607 CIRCUIT BOARD AND ELECTRONIC DEVICE
A circuit board includes an insulating substrate; a metal circuit sheet joined to a first principal surface of the insulating substrate; and a heat dissipating...
2017/0352606 BORON NITRIDE NANOTUBE ENHANCED ELECTRICAL COMPONENTS
Aligned high quality boron nitride nanotubes (BNNTs) can be incorporated into groups and bundles and placed in electronic and electrical components (ECs) to...
2017/0352605 Lighting device using short thermal path cooling technology and other device cooling by placing selected...
A novel heat sinking technology, uniquely adaptive to LED lighting devices in a generally LED array format containing multiple openings on said heat sink's...
2017/0352604 Semiconductor Device and Power Conversion Device Using Same
In order to improve productivity of a semiconductor device, while improving stability of the blocking voltage of the semiconductor device, this semiconductor...
2017/0352603 ELECTRONIC COMPONENT PACKAGE INCLUDING SEALING RESIN LAYER, METAL MEMBER, CERAMIC SUBSTRATE, AND ELECTRONIC...
An electronic component package includes: a sealing resin layer; a metal member buried therein and including a die bond portion and a terminal electrode...
2017/0352602 Sensor for a Semiconductor Device
A semiconductor arrangement is presented. The semiconductor arrangement comprises a semiconductor body, the semiconductor body including a semiconductor drift...
2017/0352601 ELECTROLUMINESCENT LIGHT SOURCE WITH AN ADJUSTED OR ADJUSTABLE LUMINANCE PARAMETER AND METHOD FOR ADJUSTING A...
An electroluminescent light source is provided with an adjusted or adjustable luminance parameter wherein: the source includes a set of segments, each segment...
2017/0352600 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING THE SAME
Provided is a semiconductor device capable of measuring a depth of removal of a silicon carbide (SiC) wafer with high accuracy through simple steps, and a...
2017/0352599 INSPECTING SURFACES
Manufacturing a device may include inspecting a surface of an inspection target device. The inspecting may include forming a metal layer on a surface of the...
2017/0352598 Double Sided NMOS/PMOS Structure and Methods of Forming the Same
A chip includes a dielectric layer having a top surface and a bottom surface, a first semiconductor layer overlying and bonded to the top surface of the...
2017/0352597 LOW RESISTANCE DUAL LINER CONTACTS FOR FIN FIELD-EFFECT TRANSISTORS (FinFETs)
A semiconductor device includes first and second gate structures on a substrate respectively corresponding to an n-type and a p-type transistor, a first...
2017/0352596 FinFETs with Strained Well Regions
A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having...
2017/0352595 METHOD FOR REDUCING N-TYPE FINFET SOURCE AND DRAIN RESISTANCE
A method of manufacturing a semiconductor device includes providing a substrate structure, the substrate structure having a semiconductor substrate including a...
2017/0352594 DISPLAY DEVICE
Disclosed is a display device that includes an array substrate that includes a display region and a first non-display region, and includes a signal line...
2017/0352593 METHOD OF SEPARATING ELECTRONIC DEVICES HAVING A BACK LAYER AND APPARATUS
A method of singulating a wafer includes providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces. The...
2017/0352592 INTEGRATED CIRCUIT STRUCTURE HAVING DEEP TRENCH CAPACITOR AND THROUGH-SILICON VIA AND METHOD OF FORMING SAME
One aspect of the disclosure relates to a method of forming an integrated circuit structure. The method may include: providing a substrate having a front side...
2017/0352591 METHOD FOR PRODUCING SELF-ALIGNED LINE END VIAS AND RELATED DEVICE
A method for producing self-aligned line end vias and the resulting device are provided. Embodiments include trench lines formed in a dielectric layer; each...
2017/0352590 INTERCONNECT STRUCTURES WITH ENHANCED ELECTROMIGRATION RESISTANCE
Interconnect structures are provided that include an intermetallic compound as either a cap or liner material. The intermetallic compound is a thermal reaction...
2017/0352589 INTERCONNECT STRUCTURES WITH ENHANCED ELECTROMIGRATION RESISTANCE
Interconnect structures are provided that include an intermetallic compound as either a cap or liner material. The intermetallic compound is a thermal reaction...
2017/0352588 EXPANSION SHEET, EXPANSION SHEET MANUFACTURING METHOD, AND EXPANSION SHEET EXPANDING METHOD
An expansion sheet is adapted to be held and expanded by an expanding apparatus when a platelike workpiece is attached to the expansion sheet. The expansion...
2017/0352587 METHOD FOR INTERRUPTING A LINE IN AN INTERCONNECT
A method for forming a pattern for an integrated circuit is disclosed. In one aspect, the method includes (a) providing a hardmask layer; (b) overlaying the...
2017/0352586 HARDMASK LAYER FOR 3D NAND STAIRCASE STRUCTURE IN SEMICONDUCTOR APPLICATIONS
Embodiments of the present disclosure provide an apparatus and methods for forming a hardmask layer that may be utilized to transfer patterns or features to a...
2017/0352585 SELF-ALIGNED QUADRUPLE PATTERNING (SAQP) FOR ROUTING LAYOUTS INCLUDING MULTI-TRACK JOGS
An interconnect structure having a pitch of less than 40 nanometers and a self-aligned quadruple patterning process for forming the interconnect structure...
2017/0352584 PATTERN FORMING METHOD
A first film having a repetitive line pattern is formed on an under film. A second film is formed on a side surface of the first film. The second film has an...
2017/0352583 FABRICATION METHOD OF A STACK OF ELECTRONIC DEVICES
This method includes the following steps: a) providing a first structure successively including a substrate, an electronic device and a dielectric layer; b)...
2017/0352582 PROCESS OF FORMING AN ELECTRONIC DEVICE INCLUDING A BOND PAD
A process of forming an electronic device including providing a substrate having a first surface and a second surface opposite the first surface; etching the...
2017/0352581 SEMICONDUCTOR WAFER AND METHOD FOR MANUFACTURING THE SAME
A semiconductor wafer in accordance with an embodiment includes: a support substrate semiconductor wafer having a first surface and a second surface opposite...
2017/0352580 Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect...
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
2017/0352579 Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect...
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
2017/0352578 Methods Of Forming One Or More Covered Voids In A Semiconductor Substrate
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
2017/0352577 Methods Of Forming One Or More Covered Voids In A Semiconductor Substrate
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
2017/0352576 SUBSTRATE PLACING TABLE
A substrate placing table, which is installed inside a processing container for processing a wafer, includes: a stage configured to place a water on an upper...
2017/0352575 Contour Pocket And Hybrid Susceptor For Wafer Uniformity
Susceptor assemblies comprising a susceptor base and a plurality of pie-shaped skins thereon are described. A pie anchor can be positioned in the center of the...
2017/0352574 APPARATUS AND METHOD FOR TREATING WAFER
An apparatus for treating a wafer is provided. The apparatus includes a platen, a chamber, an etch gas supplier and a tilting mechanism. The chamber has at...
2017/0352573 SUBSTRATE PROCESSING APPARATUS
It is an object of the present invention to provide a high-flatness substrate holding table. According to a first aspect, a substrate processing apparatus is...
2017/0352572 Wafer expander
An apparatus for expanding chips of a wafer, wherein the apparatus comprises an expansion mechanism configured for expanding a tape on which the chips of the...
2017/0352571 Method for manufacturing a handling device and method for reversible bonding using such a device
A method for manufacturing a handling device includes depositing a single layer of an adhesive on a first surface of a first wafer; depositing an antiadhesive...
2017/0352570 CIRCULAR SUPPORT SUBSTRATE FOR SEMICONDUCTOR
An object of the present invention is to provide a circular support substrate that allows for positioning based solely on its outer periphery shape. As a means...
2017/0352569 ELECTROSTATIC CHUCK HAVING PROPERTIES FOR OPTIMAL THIN FILM DEPOSITION OR ETCH PROCESSES
A heated support assembly is disclosed which includes a body comprising aluminum nitride doped with magnesium oxide having a volume resistivity of about...
2017/0352568 HIGH POWER ELECTROSTATIC CHUCK WITH APERTURE-REDUCING PLUG IN A GAS HOLE
An electrostatic chuck is described to carry a workpiece for processing such as high power plasma processing. In embodiments, the chuck includes a top plate to...
2017/0352567 HIGH POWER ELECTROSTATIC CHUCK DESIGN WITH RADIO FREQUENCY COUPLING
An electrostatic chuck is described that has radio frequency coupling suitable for use in high power plasma environments. In some examples, the chuck includes...
2017/0352566 WORKPIECE CARRIER FOR HIGH POWER WITH ENHANCED EDGE SEALING
A workpiece carrier suitable for high power processes is described. It may include a puck to carry the workpiece, a plate bonded to the puck by an adhesive, a...
2017/0352565 WORKPIECE CARRIER WITH GAS PRESSURE IN INNER CAVITIES
A workpiece carrier suitable for high power processes is described. It may include a top plate to support a workpiece, a lift pin to lift a workpiece from a...
2017/0352563 SYSTEMS AND METHODS FOR WAFER ALIGNMENT
Various embodiments of aligning wafers are described herein. In one embodiment, a photolithography system aligns a wafer by averaging individual via locations....
2017/0352562 DODECADON TRANSFER CHAMBER AND PROCESSING SYSTEM HAVING THE SAME
A transfer chamber for a processing system suitable for processing a plurality of substrates and a method of using the same is provided. The transfer chamber...
2017/0352561 METHOD FOR LAMINATING GLASS PANELS AND VACUUM LAMINATION DEVICE USING SAME
A method for laminating glass panels includes (1) providing a TFT substrate and a CF substrate to be laminated, in which the CF substrate is coated with a seal...
2017/0352560 SUBSTRATE PROCESSING METHOD
A substrate processing method includes a first process of supplying a first gas to a substrate; and a second process of supplying a second gas to the substrate...
2017/0352559 FLUORINE CONTAMINATION CONTROL IN SEMICONDUCTOR MANUFACTURING PROCESS
A method of forming a semiconductor device includes forming a fin over a substrate, forming a polysilicon gate structure over the fin, and replacing the...
2017/0352558 ROTARY PLASMA ELECTRICAL FEEDTHROUGH
The present disclosure generally relates to methods and apparatus for facilitating electrical feedthrough in plasma processing chambers. The apparatus includes...
2017/0352557 METHOD FOR WAFER OUTGASSING CONTROL
Embodiments disclosed herein generally relate to methods for controlling substrate outgassing such that hazardous gasses are eliminated from a surface of a...
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