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Patent # Description
2017/0351645 SCALABLE CONTENT RENDERING
The presently disclosed subject matter includes a computer-implemented system and method for receiving content from another computer device and dynamically...
2017/0351644 Advertisement Filtering Method and Device
An advertisement filtering method and device. The method comprises: access a web page by using a browser, acquire a selector of an advertisement element...
2017/0351643 SYSTEM FOR AUTOMATICALLY DISPLAYING PAGES OF A DIGITAL EDITION AND COMPUTER IMPLEMENTED METHOD FOR SAME
A system for automatically displaying pages of a digital edition while at least some of the pages are concurrently being edited on an editing system. The...
2017/0351642 EXECUTION ENGINE FOR EXECUTING SINGLE ASSIGNMENT PROGRAMS WITH AFFINE DEPENDENCIES
The execution engine is a new organization for a digital data processing apparatus, suitable for highly parallel execution of structured line-grain parallel...
2017/0351641 SCATTER USING INDEX ARRAY AND FINITE STATE MACHINE
Methods and apparatus are disclosed using an index array and finite state machine for scatter/gather operations. Embodiment of apparatus may comprise: decode...
2017/0351640 STANDARDIZED RETIMER
A retimer device is presented with a retimer with an array of connectors on a surface of the device that are configured to form a ball grid array to...
2017/0351639 REMOTE MEMORY ACCESS USING MEMORY MAPPED ADDRESSING AMONG MULTIPLE COMPUTE NODES
An example method for facilitating remote memory access with memory mapped addressing among multiple compute nodes is executed at an input/output (IO) adapter...
2017/0351638 USB TYPE-C ADAPTER MODULE AND ACTIVATING METHOD FOR THE SAME
A module comprising a USB Type-C receptacle, a USB Type-C plug and a logic unit is disclosed. A power pin of the receptacle is connected with another power pin...
2017/0351637 DEVICES, SYSTEMS, AND METHODS OF REDUCING CHIP SELECT
Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a...
2017/0351636 MEMORY AND METHOD FOR OPERATING A MEMORY WITH INTERRUPTIBLE COMMAND SEQUENCE
A memory device includes command logic allowing for a command protocol allowing interruption of a first command sequence, such as a page write sequence, and...
2017/0351635 System Transparent Retimer
A protocol transparent retimer circuit monitors certain link layer control signals, detects far-end receiver parameters of the link partners, and detects...
2017/0351634 SYSTEMS AND METHODS FOR DESERIALIZING DATA
A digital communication interface includes a deserializer module, a gearbox module, and a parallel communication channel connecting the gearbox module to the...
2017/0351633 MODIFICATIONS TO A STREAM PROCESSING TOPOLOGY DURING PROCESSING OF A DATA STREAM
A method, a computing system, and a non-transitory machine readable storage medium containing instructions for managing a stream processing topology are...
2017/0351632 INTERCONNECT FOR SHARED CONTROL ELECTRONICS
A mass data storage system includes a number of communicatively coupled storage drives powered and controlled by shared control electronics. The shared control...
2017/0351631 METHODS AND APPARATUSES FOR PROVIDING DATA RECEIVED BY A STATE MACHINE ENGINE
An apparatus can include a first state machine engine configured to receive a first portion of a data stream from a processor and a second state machine engine...
2017/0351630 CONFIGURING WIRELESS COMMUNICATIONS ACCORDING TO MULTIPLE COMMUNICATION PROTOCOLS
A method for communicating between a combo-endpoint device, wireless router and a wireless communication device includes monitoring communication patterns of...
2017/0351629 AUTOMATIC MULTI-HOST SWITCHING FOR MULTIPLE INPUT DEVICES
In some embodiments, a computer-implemented method includes receiving an input signal (e.g., cursor movement) from an input device communicatively paired with...
2017/0351628 LOGIC COMPONENT SWITCH
The present disclosure relates generally to semiconductor memory and methods, and more particularly, to apparatuses, and methods for controlling logic die...
2017/0351627 DYNAMIC RANDOM ACCESS MEMORY (DRAM) COMPONENT FOR HIGH-PERFORMANCE, HIGH-CAPACITY REGISTERED MEMORY MODULES
The embodiments described herein describe technologies of dynamic random access memory (DRAM) components for high-performance, high-capacity registered memory...
2017/0351626 MULTI-LEVEL DATA CACHE AND STORAGE ON A MEMORY BUS
This invention provides a system having a processor assembly interconnected to a memory bus and a memory-storage combine, interconnected to the memory bus. The...
2017/0351625 TERMINATION SCHEMES FOR MULTI-RANK MEMORY BUS ARCHITECTURES
A multi-rank memory bus architecture is provided in which an active DRAM is unterminated and an inactive DRAM terminates to increase the data eye width at the...
2017/0351624 Solid state drive control device and method
The present invention discloses a solid state drive (SSD) control device including: a multi-interface compatible physical layer circuit operable to generate a...
2017/0351623 DEVICE PROXY AND CONTROL METHOD
[Problem] To reduce processing load on the CPU driving an OS. [Solution] This device is provided with a multicore microprocessor unit (21) capable of...
2017/0351622 SELF-ENABLED BUS CONFLICT DETECTION CIRCUIT
A bus contention detection circuit includes a delay unit having an input terminal for receiving an output signal of an I/O driver, a duty cycle adjustment unit...
2017/0351621 ELECTRONIC TOOL AND METHODS WITH AUDIO FOR MEETINGS
An electronic meeting tool and method for communicating arbitrary media content from users at a meeting comprises a node configuration means adapted to operate...
2017/0351620 Caching Framework for Big-Data Engines in the Cloud
The present invention is generally directed to a caching framework that provides a common abstraction across one or more big data engines, comprising a cache...
2017/0351619 DEMOTE SCAN PROCESSING TO DEMOTE TRACKS FROM CACHE
Provided are a computer program product, system, and method demote scan processing to demote tracks from cache. Tracks in the storage stored in the cache are...
2017/0351618 INVOKING DEMOTE THREADS ON PROCESSORS TO DEMOTE TRACKS INDICATED IN DEMOTE READY LISTS FROM A CACHE WHEN A...
Provided are a computer program product, system, and method for invoking demote threads on processors to demote tracks from a cache. A plurality of demote...
2017/0351617 INFORMATION PROCESSING DEVICE, INFORMATION PROCESSING METHOD, AND NON-TRANSITORY COMPUTER-READABLE RECORDING...
An information processing device, includes: a reconfigurable integrated circuit that, by being loaded with code expressing a configuration of a circuit,...
2017/0351616 System and Method for Sleeping States Using Non-Volatile Memory Components
Sleep modes use non-volatile dual inline memory modules (NVDIMMs) to reduce electrical power and execution times. An S3 suspend-to-RAM, for example, may store...
2017/0351615 CACHE MANAGEMENT
It is determined that a cache operation relating to the transfer of data between a cache memory and a data storage system is required. A state of a utilization...
2017/0351614 NON-VOLATILE MEMORY CONTROLLER CACHE ARCHITECTURE WITH SUPPORT FOR SEPARATION OF DATA STREAMS
A system, according to one embodiment, includes: non-volatile memory; a non-volatile memory controller having a cache; and logic integrated with and/or...
2017/0351613 PRESERVATION OF MODIFIED CACHE DATA IN LOCAL NON-VOLATILE STORAGE FOLLOWING A FAILOVER
A dual-server based storage system maintains a first cache and a first non-volatile storage (NVS) in a first server, and a second cache and a second NVS in a...
2017/0351612 DATA PROCESSING METHOD AND DEVICE IN CACHE COHERENCE DIRECTORY ARCHITECTURE
The embodiment of the disclosure discloses a data processing method and device in a cache coherence directory architecture. The method includes that allocating...
2017/0351611 INVOKING INPUT/OUTPUT (I/O) THREADS AND DEMOTE THREADS ON PROCESSORS TO DEMOTE TRACKS FROM A CACHE
Provided are a computer program product, system, and method for invoking Input/Output (I/O) threads and demote threads on processors to demote tracks from a...
2017/0351610 MODULIZATION OF CACHE STRUCTURE IN MICROPROCESSOR
Embodiments of the present disclosure support implementation of a Level-1 (L1) cache in a microprocessor based on independently accessed data and tag arrays....
2017/0351609 STORAGE DRIVE DEPENDENT TRACK REMOVAL IN A CACHE FOR STORAGE
In one embodiment, storage drive dependent track removal processing logic performs destage tasks for tracks cached in a cache as a function of whether the...
2017/0351608 HOST DEVICE
According to one embodiment, a host device is provided. The host device includes a processor that stores a log of a file in plurality of storages using a log...
2017/0351607 Multi-Section Garbage Collection
The embodiments relate to a method for managing a garbage collection process. The method includes executing a garbage collection process on a memory block of...
2017/0351606 PERSISTENT MEMORY GARBAGE COLLECTION
According to an example, persistent memory garbage collection may include determining whether termination of a program is based on a specified termination of...
2017/0351605 ADDRESS TRANSLATION FOR A NON-VOLATILE MEMORY STORAGE DEVICE
Techniques are described for accessing data from a storage device. In one example, the storage device may include a storage medium comprising non-volatile...
2017/0351604 HOST AND GARBAGE COLLECTION WRITE RATIO CONTROLLER
A method includes obtaining an average number of valid pages per block of the solid state storage device, obtaining an average number of invalid pages per...
2017/0351603 LAZY REAL TIME GARBAGE COLLECTION METHOD
A method for garbage collection in a NAND flash memory system is disclosed. The method includes the steps of receiving a data request task in the NAND flash...
2017/0351602 STORAGE DEVICE AND NON-VOLATILE MEMORY DEVICE
To determine whether or not to data is compressed at a timing when a non-volatile memory device receives the data from a host apparatus. A storage controller...
2017/0351601 COMPUTER SYSTEM, COMPUTER, AND METHOD
An allocation request for requesting allocation of a target virtual area with respect to target data issued to a system program includes a target ID...
2017/0351600 SYSTEM AND METHOD OF TRANSFER OF CONTROL BETWEEN MEMORY LOCATIONS
Disclosed are system and method for controlling execution of a program. An example method includes determining a memory sector for storing at least a portion...
2017/0351599 AUTOMATICALLY RERUNNING TEST EXECUTIONS
Example implementations relate to automatically rerunning test executions. Some implementations may capture data during executions of a test. The data may...
2017/0351598 OPTIMIZATIONS FOR REGRESSION TRACKING AND TRIAGING IN SOFTWARE TESTING
An example system configured to perform regression tracking and triaging includes a processor and memory coupled with the processor. The memory is configured...
2017/0351597 IDENTIFYING AND ISOLATING LIBRARY CODE IN SOFTWARE APPLICATIONS
A computer system, method, and computer readable product are provided for identifying and isolating library code that has been obfuscated in software...
2017/0351596 TECHNIQUES FOR TRAVERSING REPRESENTATIONS OF SOURCE CODE
Methods, apparatus, and systems for traversing a representation of an application source code, such as an abstract syntax tree (AST), are disclosed. Steps for...
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