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Patent # Description
2017/0358574 INTEGRATED CIRCUITS WITH CAPACITORS AND METHODS FOR PRODUCING THE SAME
Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a first capacitor with a first...
2017/0358573 SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
A semiconductor device includes a first gate pattern and a second gate pattern on a substrate, the first gate pattern having a first height and the second gate...
2017/0358572 Structure and Method for Cooling Three-Dimensional Integrated Circuits
A structure and method for cooling a three-dimensional integrated circuit (3DIC) are provided. A cooling element is configured for thermal connection to the...
2017/0358571 DISPLAY PANEL AND DISPLAY DEVICE INCLUDING THE SAME
A display panel is disclosed, which includes: a substrate; plural scan lines disposed on the substrate and extending along a first direction; a first...
2017/0358570 INTEGRATED CIRCUIT WITH TRIPLE GUARD WALL POCKET ISOLATION
A semiconductor device includes a substrate having a semiconductor surface doped a second dopant type with a buried layer (BL) doped a first dopant type....
2017/0358569 ELECTROSTATIC DISCHARGE DEVICE
An integrated circuit device includes at least two epitaxially grown active regions grown onto a substrate, the active regions being placed between a first...
2017/0358568 POSITIVE STRIKE SCR, NEGATIVE STRIKE SCR, AND A BIDIRECTIONAL ESD STRUCTURE THAT UTILIZES THE POSITIVE STRIKE...
A first silicon controlled rectifier has a breakdown voltage in a first direction and a breakdown voltage in a second direction. A second silicon controlled...
2017/0358567 TRANSIENT SUPPRESSING CIRCUIT ARRANGEMENTS
Transient suppression circuit arrangements are disclosed. In one implementation of a transient suppression circuit, at least one avalanche diode is coupled in...
2017/0358566 Systems and Methods for a Sequential Spacer Scheme
Semiconductor devices disclosed herein have minimum spacings that correlate with spacer widths. An exemplary semiconductor device includes a substrate and a...
2017/0358564 SEMICONDUCTOR PACKAGE
A semiconductor package may be composed of a variety of different types of semiconductor chips of different sizes and support structures stacked within the...
2017/0358563 PIXEL STRUCTURE, DISPLAY DEVICE INCLUDING THE PIXEL STRUCTURE, AND METHOD OF MANUFACTURING THE PIXEL STRUCTURE
A pixel structure, a display device, and a method of manufacturing a pixel structure, the pixel structure including a base substrate; at least one first...
2017/0358562 INTEGRATED DISPLAY SYSTEM WITH MULTI-COLOR LIGHT EMITTING DIODES (LEDs)
A display system is disclosed. The display system comprises a light emitting diode (LED) device and a backplane (BP) device. The LED device comprises a...
2017/0358561 LED LEADFRAME AND LED PACKAGING STRUCTURE
A LED leadframe and a LED packaging structure adopting the same are provided. The LED leadframe includes an insulating substrate, a first electrode pad and a...
2017/0358560 Semiconductor Package Using A Coreless Signal Distribution Structure
A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at...
2017/0358559 METHODS OF MANUFACTURING A SEMICONDUCTOR DEVICE PACKAGE INCLUDING A CONTROLLER ELEMENT
Semiconductor device packages include a stack of semiconductor memory devices positioned over an interposer substrate, a controller element, and a...
2017/0358558 SEMICONDUCTOR PACKAGE
A semiconductor package includes a first semiconductor chip including a through silicon via in the first semiconductor chip and a first trench portion in an...
2017/0358557 PACKAGE-ON-PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF
A POP structure includes a first package structure, an interposer, and a second package structure. The first package structure includes a first carrier, a...
2017/0358556 Semiconductor device assembly with through-mold cooling channel formed in encapsulant
Semiconductor device assemblies having stacked semiconductor dies and thermal transfer devices that include vapor chambers are disclosed herein. In one...
2017/0358555 STACKED SEMICONDUCTOR PACKAGE WITH COMPLIANT CORNERS ON FOLDED SUBSTRATE
One or more embodiments are directed to stacked packages, such as Package-on-Package (PoP) packages, that are stacked on a flexible folded substrate. The...
2017/0358554 WAFER STACKING FOR INTEGRATED CIRCUIT MANUFACTURING
A method of manufacturing integrated devices, and a stacked integrated device are disclosed. In an embodiment, the method comprises providing a substrate;...
2017/0358553 WAFER-TO-WAFER BONDING STRUCTURE
A wafer-to-wafer bonding structure includes a first wafer including a first conductive pad in a first insulating layer and a first barrier layer surrounding a...
2017/0358552 Silicon Interposer Sandwich Structure for ESD, EMC, and EMC Shielding and Protection
A interposer sandwich structure comprises a top interposer and a bottom interposer enclosing an integrated circuit electronic device that includes means for...
2017/0358551 Hybrid Bonding Systems and Methods for Semiconductor Wafers
Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a...
2017/0358550 CONTROL WIRE CLAMP AND LOOP SYSTEMS AND METHODS
The disclosed technology includes a control wire clamp for securing a control member, such as a control wire, in place. The default state of the control wire...
2017/0358549 MULTILAYER SUBSTRATE
Provided is a multilayer substrate including laminated semiconductor substrates each having a penetrating hole (hereinafter referred to as through hole) having...
2017/0358548 ELECTRONIC COMPONENT PACKAGE AND ELECTRONIC DEVICE INCLUDING THE SAME
An electronic component package includes an electronic component, a redistribution layer electrically connected to the electronic component and having terminal...
2017/0358547 SEMICONDUCTOR DEVICES INCLUDING CONDUCTIVE PILLARS
A method of forming a conductive material on a semiconductor device. The method comprises removing at least a portion of a conductive pad within an aperture in...
2017/0358546 FLIP CHIP
A flip chip includes a substrate, an electrode pad layer stacked over the substrate, a passivation layer stacked at both ends of the electrode pad layer, an...
2017/0358545 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
A pad is disposed on a substrate. A bump structure is disposed on the pad and electrically connected to the pad. The bump structure includes a first copper...
2017/0358544 SEMICONDUCTOR ASSEMBLY WITH PACKAGE ON PACKAGE STRUCTURE AND ELECTRONIC DEVICE INCLUDING THE SAME
A semiconductor assembly with a package on package (POP) structure includes a first semiconductor package having a first lower substrate, a first upper...
2017/0358543 HEAT-DISSIPATING SEMICONDUCTOR PACKAGE FOR LESSENING PACKAGE WARPAGE
A heat-dissipating semiconductor package includes a substrate, a chip, a first encapsulation body, a second encapsulation body and a heat sink. The substrate...
2017/0358542 STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE WITH LID
Structures and formation methods of a chip package are provided. The chip package includes a substrate and a semiconductor die over a surface of the substrate....
2017/0358541 TILED-STRESS-ALLEVIATING PAD STRUCTURE
Structure and method for reducing thermal-mechanical stresses generated for a semiconductor device are provided, which includes a tiled-stress-alleviating pad...
2017/0358540 SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING THE SAME
Semiconductor packages and a methods for manufacturing a semiconductor package are provided. The method includes providing a package including a substrate, a...
2017/0358539 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD
A mark is formed over the surface of a silicon substrate. The mark includes a silicon oxide film, in which a plurality of rectangular groove patterns are...
2017/0358538 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
A marking structure where marking visibility is improved is provided. In a semiconductor device having a marking structure, the marking structure includes: a...
2017/0358537 METHOD OF WAFER DICING FOR BACKSIDE METALLIZATION
Method embodiments of wafer dicing for backside metallization are provided. One method includes: applying dicing tape to a front side of a semiconductor wafer,...
2017/0358536 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND CORRESPONDING DEVICE
In one embodiment, a method of manufacturing semiconductor devices including metallizations (e.g. a Re-Distribution Layer--RDL metallizations) includes...
2017/0358535 SEMICONDUCTOR PACKAGES
Provided are a semiconductor package. The semiconductor package comprises a redistribution substrate, an interconnect substrate on the redistribution substrate...
2017/0358534 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole; an...
2017/0358533 Low-Temperature Diffusion Doping of Copper Interconnects Independent of Seed Layer Composition
Low-temperature techniques for doping of Cu interconnects based on interfacially-assisted thermal diffusion are provided. In one aspect, a method of forming...
2017/0358532 Electronic Component Of Integrated Circuitry And A Method Of Forming A Conductive Via To A Region Of...
An electronic component of integrated circuitry comprises a substrate comprising at least two terminals. Material of one of the terminals has an upper surface....
2017/0358531 Interconnection Structure, Fabricating Method Thereof, and Semiconductor Device Using the Same
A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on...
2017/0358530 SEMICONDUCTOR DEVICE
A semiconductor device includes: a semiconductor substrate having a main surface; a first insulating film formed in a convex shape and provided on the main...
2017/0358529 FORMING A STACKED CAPACITOR
Stacked capacitor structures using TSVs are provided. In one aspect, a stacked capacitor structure includes: a first substrate having at least one first...
2017/0358528 PACKAGE SUBSTRATE HAVING NONCIRCULAR INTERCONNECTS
Package substrates including conductive interconnects having noncircular cross-sections, and integrated circuit packages incorporating such package substrates,...
2017/0358527 INTERPOSER, SEMICONDUCTOR PACKAGE STRUCTURE, AND SEMICONDUCTOR PROCESS
An interposer includes an interconnection structure and a redistribution layer. The interconnection structure includes a metal layer, at least one metal via...
2017/0358526 MOLDED INTERCONNECT DEVICE, MANUFACTURING METHOD FOR MOLDED INTERCONNECT DEVICE, AND CIRCUIT MODULE
A molded interconnect device adapted to form a three-dimensional circuit by using laser beams includes: a main body on which the three-dimensional circuit is...
2017/0358525 FLEXIBLE SEMICONDUCTOR DEVICE WITH GRAPHENE TAPE
A flexible semiconductor device includes a first tape having bonding pads and conductive traces formed. A semiconductor die having a bottom surface is attached...
2017/0358524 RING-FRAME POWER PACKAGE
The present disclosure relates to a ring-frame power package that includes a thermal carrier, a spacer ring residing on the thermal carrier, and a ring...
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