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Patent # Description
2017/0358523 LEADFRAME STRIP WITH VERTICALLY OFFSET DIE ATTACH PADS BETWEEN ADJACENT VERTICAL LEADFRAME COLUMNS
A leadframe strip for use in making leaded integrated circuit packages includes a plurality of integrally connected leadframes that each have a die attach pad...
2017/0358522 SEMICONDUCTOR DEVICE
Provided is a semiconductor device capable of having simple wiring in mounting the semiconductor device. The semiconductor device includes at least one...
2017/0358521 MAGNETIC SENSOR
A magnetic sensor includes a semiconductor element, a lead frame, a bonding wire, and a package. The lead frame includes a die pad to which the semiconductor...
2017/0358520 CHIP-ON-FILM PACKAGE AND DISPLAY DEVICE INCLUDING THE SAME
A chip-on-film (COF) package includes a film, a driver integrated circuit (IC) chip disposed on the film, an electrode pad disposed on an edge of the film, and...
2017/0358519 Semiconductor Device and Method of Fabricating the Same
A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a first interlayer insulating layer including a...
2017/0358518 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME
A semiconductor package includes a first semiconductor component, a second semiconductor component, and a connecting element. The first semiconductor component...
2017/0358517 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A semiconductor device including a semiconductor chip and a heat dissipation unit (heat sink) is configured as follows. The heat dissipation unit (heat sink)...
2017/0358516 POWER MODULE
A power module is disclosed. The power module includes a first substrate, a first metal layer, at least one conductive structure and at least one power device....
2017/0358515 SUBSTRATE WITH INTEGRATED HEAT SPREADER
The present disclosure relates to a substrate with an integrated heat spreader. The disclosed substrate includes a substrate core, at least one connecting...
2017/0358514 SEMICONDUCTOR DEVICE AND LEAD FRAME THEREFOR
A semiconductor device includes a semiconductor die having a first side having a first terminal and an opposite second side having at least two second...
2017/0358513 CIRCUIT BOARD AND ELECTRONIC DEVICE PROVIDED WITH SAME
A circuit board includes: a base body formed of ceramics or sapphire, the base body being provided with a through hole which penetrates therethrough from one...
2017/0358512 SEMICONDUCTOR DEVICE
A semiconductor device includes: a first power semiconductor element; a second power semiconductor element that is connected in parallel with the first power...
2017/0358511 THERMALLY ENHANCED SEMICONDUCTOR PACKAGE WITH THERMAL ADDITIVE AND PROCESS FOR MAKING THE SAME
The present disclosure relates to a thermally enhanced semiconductor package, which includes a module substrate, a thinned flip chip die over the substrate, a...
2017/0358510 WAFER-LEVEL CHIP-SCALE PACKAGE INCLUDING POWER SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF
A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second...
2017/0358509 PROCESS OF ENCAPSULATING ELECTRONIC COMPONENTS
In order to carry out the encapsulation of electronic components, the invention proposes to cover the electronic components (7) with a heat-polymerisable...
2017/0358508 MOTHERBOARD OF ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF
Embodiments of the present disclosure provide a motherboard of an array substrate and a manufacturing method thereof. The motherboard of an array substrate...
2017/0358507 FABRICATION OF SACRIFICIAL INTERPOSER TEST STRUCTURE
A sacrificial interposer test structure including a release layer, a dummy layer on the release layer, one or more conductive pads embedded in the dummy layer,...
2017/0358506 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Provided is a technique capable of obtaining a satisfactory yield for a semiconductor device with an air gap. The technique includes a method of manufacturing...
2017/0358505 METHODS FOR MANUFACTURING A DISPLAY DEVICE
Methods for manufacturing a display device are provided. A representative method includes: providing a thin film transistor (TFT) substrate having a plurality...
2017/0358504 PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD
A plasma processing method of processing layer structure previously formed on an upper surface of a wafer disposed in a processing chamber within a vacuum...
2017/0358503 DISPLAY DEVICE AND METHOD OF MANUFACTURING THE DISPLAY DEVICE
A display device includes a substrate, a first transistor, a second transistor and a conductive connection portion disposed on the substrate. The first...
2017/0358502 METHOD FOR PRODUCING ON THE SAME TRANSISTORS SUBSTRATE HAVING DIFFERENT CHARACTERISTICS
There is provided a method for producing on a same substrate at least one first transistor and at least one second transistor that have different ...
2017/0358501 HIGH GAIN TRANSISTOR FOR ANALOG APPLICATIONS
An analog high gain transistor is disclosed. The formation of the analog high gain transistor is highly compatible with existing CMOS processes. The analog...
2017/0358500 Horizontal Gate-All-Around Device Having Wrapped-Around Source and Drain
Various semiconductor devices, such as horizontal gate-all-around devices, and methods of fabricating such are disclosed herein. An exemplary semiconductor...
2017/0358499 ELECTRONIC DEVICE
An electronic device includes at least two boards and support pillars. The at least two boards include hole portions. The support pillars inserted into the...
2017/0358498 FORMING INSULATOR FIN STRUCTURE IN ISOLATION REGION TO SUPPORT GATE STRUCTURES
A method for forming the semiconductor device that includes forming a plurality of composite fin structures across a semiconductor substrate including an...
2017/0358497 FABRICATION OF A VERTICAL TRANSISTOR WITH SELF-ALIGNED BOTTOM SOURCE/DRAIN
A method of forming a vertical fin field effect transistor (vertical finFET) with a self-aligned bottom source/drain, including forming a doped layer on a...
2017/0358496 STRESS MEMORIZATION TECHNIQUE FOR STRAIN COUPLING ENHANCEMENT IN BULK FINFET DEVICE
A method for forming strained fins includes etching trenches in a bulk substrate to form fins, filling the trenches with a dielectric fill and recessing the...
2017/0358495 EPITAXIAL STRUCTURE OF GA-FACE GROUP III NITRIDE, ACTIVE DEVICE, AND METHOD FOR FABRICATING THE SAME
The present invention provides an epitaxial structure of Ga-face group III nitride, its active device, and the method for fabricating the same. The epitaxial...
2017/0358494 PLASMA DICING OF SILICON CARBIDE
A method of forming a semiconductor device includes forming an active region in a first side of a silicon carbide substrate, the silicon carbide substrate...
2017/0358493 THROUGH SUBSTRATE VIA STRUCTURE FOR NOISE REDUCTION
A semiconductor device includes a substrate and a through substrate via structure. The substrate has a through via hole. The through substrate via structure is...
2017/0358492 SELF ALIGNED CONDUCTIVE LINES
A method for forming conductive lines on a wafer comprises forming a first sacrificial mandrel and a second sacrificial mandrel. Spacers are formed adjacent to...
2017/0358491 SEMICONDUCTOR TRANSISTOR DEVICE AND FABRICATION METHOD THEREOF
A semiconductor transistor device includes a substrate having an active area and a trench isolation region surrounding the active area, a gate oxide layer, a...
2017/0358490 SEAM-HEALING METHOD UPON SUPRA-ATMOSPHERIC PROCESS IN DIFFUSION PROMOTING AMBIENT
Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the...
2017/0358489 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
It is to provide a manufacturing method of a semiconductor device including the following steps of: preparing a semiconductor substrate having a silicon...
2017/0358488 Method of Sealing Open Pores on Surface of Porous Dielectric Material Using iCVD Process
Provided are methods of sealing open pores of a surface of a porous dielectric material using an initiated chemical vapor deposition (iCVD) process. In one...
2017/0358487 SELF ALIGNED CONDUCTIVE LINES
A method for forming conductive lines on a wafer comprises forming a first hardmask, a planarizing layer, a second hardmask, a layer of sacrificial mandrel...
2017/0358486 METAL-GRAPHENE HETEROJUNCTION METAL INTERCONNECTS, METHOD OF FORMING THE SAME, AND SEMICONDUCTOR DEVICE...
Disclosed herein are a metal-graphene heterojunction metal interconnect, a method of forming the same, and a semiconductor device including the same. The...
2017/0358485 SEMICONDUCTOR STRUCTURE
A semiconductor structure includes a substrate, first and second conductors, a passivation material, and a passivation sidewall block. The first and second...
2017/0358484 HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING A CHARGE TRAPPING LAYER FORMED BY He-N2 CO-IMPLANTATION
A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a...
2017/0358483 Oxidative Volumetric Expansion Of Metals And Metal Containing Compounds
Methods comprising forming a film on at least one feature of a substrate surface are described. The film is expanded to fill the at least one feature and cause...
2017/0358482 SELECTIVE DEPOSITION OF METALLIC FILMS
Metallic layers can be selectively deposited on one surface of a substrate relative to a second surface of the substrate. In some embodiments, the metallic...
2017/0358481 Multi-Barrier Deposition for Air Gap Formation
A method includes forming a first conductive line and a second conductive line in a dielectric layer, etching a portion of the dielectric layer to form a...
2017/0358479 SUBSTRATE TRANSFER DEVICE AND SUBSTRATE TRANSFER METHOD
Generation of dust from a peripheral portion of a substrate can be suppressed, and a processed substrate can be suppressed from being adversely affected by a...
2017/0358478 MASKLESS PARALLEL PICK-AND-PLACE TRANSFER OF MICRO-DEVICES
An apparatus for positioning micro-devices on a destination substrate includes a first support to hold a destination substrate, a second support to provide or...
2017/0358477 SEMICONDUCTOR DEVICE SUBSTRATE, SEMICONDUCTOR DEVICE WIRING MEMBER AND METHOD FOR MANUFACTURING THEM, AND...
A semiconductor device substrate and wiring member including a first noble metal plating layer to become internal terminals is formed at predetermined sites on...
2017/0358476 SINTERED BODY AND ELECTROSTATIC CHUCK
A sintered body includes a ceramic substrate including sintered oxide particles, a through-hole formed in the ceramic substrate such that the side surfaces of...
2017/0358475 ELECTROSTATIC CHUCK AND PLASMA APPARATUS FOR PROCESSING SUBSTRATES HAVING THE SAME
An electrostatic chuck assembly includes a dielectric plate having an absorption electrode to generate an electrostatic force, the dielectric plate securing a...
2017/0358474 Wafer Support Device and Method for Removing Lift Pin Therefrom
A wafer support device includes a susceptor, at least one lift pin, at least one lift pin support base and at least one pad. The susceptor has a bottom surface...
2017/0358473 ASSEMBLING DEVICE USED FOR SEMICONDUCTOR EQUIPMENT
The present invention is directed to an assembling device used for semiconductor equipment. The assembling device includes a chamber lid, a ceiling, a...
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