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Patent # Description
2017/0365728 TANDEM SOLAR CELL MODULE
A tandem solar cell module includes a transparent substrate, a first solar cell unit, and a second solar cell unit disposed between the transparent substrate...
2017/0365727 SOLAR CELL MODULE
A solar cell module includes: a light-diffusing member adjacent to a solar cell; a tab line disposed on front surfaces of solar cells and having a...
2017/0365725 ELECTRICAL AND OPTICAL VIA CONNECTIONS ON A SAME CHIP
The present disclosure relates to semiconductor structures and, more particularly, to electrical and optical via connections on a same chip and methods of...
2017/0365724 Transparent Conductive Oxide In Silicon Heterojunction Solar Cells
Devices and methods for reducing optical losses in transparent conductive oxides (TCOs) used in silicon heterojunction (SHJ) solar cells while enhancing series...
2017/0365723 VACUUM PACKAGE, ELECTRONIC DEVICE, AND VEHICLE
A vacuum package includes a substrate, a pair of through electrodes that penetrates the substrate, each of the pair of the trough electrodes having first end...
2017/0365722 PROCESS OF FORMING METAL-INSULATOR-METAL (MIM) CAPACITOR
A metal-insulator-metal (MIM) capacitor and a process of forming the same are disclosed. The process includes steps of: forming a lower electrode that provides...
2017/0365721 DIODES AND FABRICATION METHODS THEREOF
Diodes and fabrication methods thereof are presented. The diodes include, for instance: a first semiconductor region disposed at least partially within a...
2017/0365720 TRANSISTOR, ELECTRONIC DEVICE, MANUFACTURING METHOD OF TRANSISTOR
Reducing the power consumption of a transistor and stably controlling its threshold value. Providing a transistor comprising a first conductive layer, a first...
2017/0365719 Negative Capacitance Field Effect Transistor
A gate structure of a negative capacitance field effect transistor (NCFET) is disclosed. The NCFET includes a gate stack disposed over a substrate. The gate...
2017/0365718 INSULATOR/METAL PASSIVATION OF MOTFT
A method of passivating a MOTFT including providing a metal oxide thin film transistor having a surface defined by spaced apart source/drain terminals...
2017/0365717 SILICON-CONTAINING, TUNNELING FIELD-EFFECT TRANSISTOR INCLUDING III-N SOURCE
Tunneling field-effect transistors including silicon, germanium or silicon germanium channels and III-N source regions are provided for low power operations. A...
2017/0365716 SEMICONDUCTOR DEVICE
A semiconductor device includes a first multi-channel active pattern, a field insulation layer disposed on the first multi-channel active pattern and including...
2017/0365715 Damage Implantation of a Cap Layer
A method for fabricating a transistor on a semiconductor wafer includes providing a partial transistor containing a gate stack, extension regions, and...
2017/0365714 PRECISE JUNCTION PLACEMENT IN VERTICAL SEMICONDUCTOR DEVICES USING ETCH STOP LAYERS
A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch...
2017/0365713 VERTICAL TRANSISTOR HAVING UNIFORM BOTTOM SPACERS
A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure that includes a fin on a semiconductor...
2017/0365712 PRECISE JUNCTION PLACEMENT IN VERTICAL SEMICONDUCTOR DEVICES USING ETCH STOP LAYERS
A semiconductor device is provided that includes a first of a source region and a drain region comprised of a first semiconductor material, wherein an etch...
2017/0365711 SEMICONDUCTOR DEVICE
There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with...
2017/0365710 LATERAL SUPER-JUNCTION MOSFET DEVICE AND TERMINATION STRUCTURE
A lateral superjunction MOSFET device includes multiple transistor cells connected to a lateral superjunction structure, each transistor cell including a...
2017/0365709 SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE,...
A semiconductor device according to an embodiment includes a SiC layer having a first and a second plane, a first SiC region of a first conductivity type,...
2017/0365708 TRENCH POWER SEMICONDUCTOR DEVICE
A trench power semiconductor device is provided. A trench gate structure of the trench power semiconductor device located in a cell trench of an epitaxial...
2017/0365707 SEMICONDUCTOR DEVICE INCLUDING FIN-FET AND MANUFACTURING METHOD THEREOF
A semiconductor device includes a first fin structure for a first fin field effect transistor (PET). The first fin structure includes a first base layer...
2017/0365706 FIELD EFFECT TRANSISTORS WITH SELF-ALIGNED EXTENSION PORTIONS OF EPITAXIAL ACTIVE REGIONS
A gate structure is formed across a single crystalline semiconductor fin. An amorphizing ion implantation is performed employing the gate structure as an...
2017/0365705 STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE WITH GATE STACKS
Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a...
2017/0365704 VERTICAL DMOS TRANSISTOR
A transistor includes a semiconductor body; a body region of a first conductivity type formed in the semiconductor body; a gate electrode formed partially...
2017/0365703 FIELD-EFFECT TRANSISTOR AND METHOD OF MAKING THE SAME
A semiconductor device includes a semiconductor substrate, a gate structure formed over the semiconductor substrate, and an epitaxial structure formed...
2017/0365702 High-Electron-Mobility Transistor Having a Buried Field Plate
A high-electron-mobility semiconductor device includes: a buffer region having first, second and third cross-sections forming a stepped lateral profile, the...
2017/0365701 Charge Trapping Prevention III-Nitride Transistor
There are disclosed herein various implementations of a charge trapping prevention III-Nitride transistor. Such a transistor may be a III-Nitride high electron...
2017/0365700 HIGH ELECTRON MOBILITY TRANSISTOR (HEMT) DEVICE AND METHOD OF MAKING THE SAME
A high electron mobility transistor (HEMT) device with epitaxial layers that include a gallium nitride (GaN) layer co-doped with silicon (Si) and germanium Ge...
2017/0365699 Low Dislocation Density III-Nitride Semiconductor Component
There are disclosed herein various implementations of a semiconductor component including a protrusion propagation body. The semiconductor component includes a...
2017/0365698 NITRIDE SEMICONDUCTOR DEVICE
A nitride semiconductor device includes: a substrate of a first conductivity type having a first surface and a second surface on a side of the substrate...
2017/0365697 SEMICONDUCTOR DEVICE
The performance of a semiconductor device is improved. An emitter electrode is coupled to a P-type body region and an N.sup.+-type emitter region of a linear...
2017/0365696 POWER SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
Provided is a power semiconductor device comprising a pair of gate electrodes respectively disposed in a first trench and a second trench spaced apart from...
2017/0365695 FABRICATION OF INTEGRATED CIRCUIT STRUCTURES FOR BIPOLOR TRANSISTORS
Methods of according to the present disclosure can include: providing a substrate including: a first semiconductor region, a second semiconductor region, and a...
2017/0365694 COMPLEMENTARY TUNNELING FET DEVICES AND METHOD FOR FORMING THE SAME
Described is an apparatus forming complementary tunneling field effect transistors (TFETs) using oxide and/or organic semiconductor material. One type of TFET...
2017/0365693 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
A transistor with stable electrical characteristics is provided. Provided is a method for manufacturing a semiconductor device that includes, over a substrate,...
2017/0365692 ASPECT RATIO TRAPPING IN CHANNEL LAST PROCESS
A method of forming the fin structure that includes forming a replacement gate structure on a channel region of the at least one replacement fin structure; and...
2017/0365691 Method of Forming a Contact
A method includes forming a first gate structure in a dielectric layer over a substrate, wherein the first gate structure includes a first gate stack and...
2017/0365690 TRANSISTOR DEVICE AND FABRICATION METHOD
Transistor devices and fabrication methods are provided. A transistor is formed by forming a dummy gate film on a substrate and doping an upper portion of the...
2017/0365689 MANUFACTURING METHOD FOR COMPOUND SEMICONDUCTOR DEVICE
A support substrate is bonded to a GaN epitaxial substrate including at least an electron transport layer and an electron supply layer grown on a growth...
2017/0365688 HETEROJUNCTION BIPOLAR TRANSISTOR FULLY SELF-ALIGNED TO DIFFUSION REGION WITH STRONGLY MINIMIZED SUBSTRATE...
Methods for manufacturing a bipolar junction transistor are provided. A method includes providing a semiconductor substrate having a trench isolation, where a...
2017/0365687 METHOD FOR MANUFACTURING AN EMITTER FOR HIGH-SPEED HETEROJUNCTION BIPOLAR TRANSISTORS
A method for manufacturing a bipolar junction transistor is provided. A layer stack is provided that comprises a semiconductor substrate having a trench...
2017/0365686 Method and Structure for FinFET Comprising Patterned Oxide and Dielectric Layer under Spacer Features
A semiconductor device includes a substrate having a fin projecting upwardly through an isolation structure over the substrate; a gate stack over the isolation...
2017/0365685 INTEGRATION OF STRAINED SILICON GERMANIUM PFET DEVICE AND SILICON NFET DEVICE FOR FINFET STRUCTURES
A method of forming a finFET transistor device includes forming a crystalline, compressive strained silicon germanium (cSiGe) layer over a substrate; masking a...
2017/0365684 Method for Forming Mask Pattern, Thin Film Transistor and Method for Forming the Same, and Display Device
A method for forming a mask pattern is provided, comprising forming a negative photoresist on a substrate; in an environment without oxygen, to performing a...
2017/0365683 POWER DEVICE HAVING A POLYSILICON-FILLED TRENCH WITH A TAPERED OXIDE THICKNESS
In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected...
2017/0365682 SOURCE AND DRAIN EPITAXIAL SEMICONDUCTOR MATERIAL INTEGRATION FOR HIGH VOLTAGE SEMICONDUCTOR DEVICES
A method of forming a semiconductor device that includes providing a first set of fin structures having a first pitch, and a second set of fin structure having...
2017/0365681 FERMI-LEVEL UNPINNING STRUCTURES FOR SEMICONDUCTIVE DEVICES, PROCESSES OF FORMING SAME, AND SYSTEMS CONTAINING SAME
An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth...
2017/0365680 GATE PATTERNING FOR AC AND DC PERFORMANCE BOOST
A method to reduce parasitic capacitance in a high-k dielectric metal gate (HKMG) transistor with raised source and drain regions (RSD) is provided including...
2017/0365679 SEMICONDUCTOR DEVICE HAVING A METAL GATE ELECTRODE STACK
A semiconductor device includes a substrate and a gate dielectric layer on the substrate. The gate dielectric layer includes a single metal oxide layer. The...
2017/0365678 METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR
An embodiment of a semiconductor device includes forming an active region that extends vertically into the semiconductor material in which the semiconductor...
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