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Patent # Description
2017/0373173 SEMICONDUCTOR DEVICE
This semiconductor device comprises an active layer that is formed of an oxide magnetic material and a porous dielectric body that contains water and is...
2017/0373172 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
An object is to reduce a capacitance value of parasitic capacitance without decreasing driving capability of a transistor in a semiconductor device such as an...
2017/0373171 INTEGRATED JFET STRUCTURE WITH IMPLANTED BACKGATE
A semiconductor device contains a JFET with a channel layer having a first conductivity type in a substrate. The JFET has a back gate having a second,...
2017/0373170 SILICIDATION OF BOTTOM SOURCE/DRAIN SHEET USING PINCH-OFF SACRIFICIAL SPACER PROCESS
A vertical fin field-effect-transistor and a method for fabricating the same. The vertical fin field-effect-transistor includes at least a substrate, a first...
2017/0373169 SEMICONDUCTOR STRUCTURE
A method for forming a semiconductor structure includes providing a semiconductor substrate having a metal gate structure formed on the semiconductor...
2017/0373168 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE
A semiconductor device includes a first semiconductor layer formed of a nitride semiconductor, on a substrate; a second semiconductor layer formed of a nitride...
2017/0373167 VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR WITH PRECISE GATE LENGTH DEFINITION
Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom...
2017/0373166 VERTICAL TRANSPORT FIELD EFFECT TRANSISTOR WITH PRECISE GATE LENGTH DEFINITION
Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom...
2017/0373165 DUAL-GATE TFT ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF
A dual-gate TFT (thin film transistor) array substrate and a manufacturing method thereof are provided. A source electrode and a drain electrode are formed on...
2017/0373164 METAL CONTACTS TO GROUP IV SEMICONDUCTORS BY INSERTING INTERFACIAL ATOMIC MONOLAYERS
Techniques for reducing the specific contact resistance of metal-semiconductor (group IV) junctions by interposing a monolayer of group V or group III atoms at...
2017/0373163 METHOD FOR MANUFACTURING HORIZONTAL-GATE-ALL-AROUND DEVICES WITH DIFFERENT NUMBER OF NANOWIRES
A method includes the following operations: (i) receiving a FET precursor including a first fin and a second fin, each of the first fin and the second fin...
2017/0373162 FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH A REDUCED CONTACT RESISTANCE
A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region,...
2017/0373161 METHOD OF FORMING A GATE CONTACT STRUCTURE AND SOURCE/DRAIN CONTACT STRUCTURE FOR A SEMICONDUCTOR DEVICE
One illustrative method disclosed includes, among other things, forming a sacrificial S/D contact structure above an S/D region of a transistor device,...
2017/0373160 SIDEWALL PROTECTIVE LAYER FOR CONTACT FORMATION
A method for forming a semiconductor device comprises forming a sacrificial gate stack on a substrate, spacers adjacent to the sacrificial gate stack, and a...
2017/0373159 FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH A REDUCED CONTACT RESISTANCE
A method of forming a vertical fin field effect transistor (vertical finFET) with an increased surface area between a source/drain contact and a doped region,...
2017/0373158 CIRCUIT CONFIGURATION AND MANUFACTURING PROCESSES FOR VERTICAL TRANSIENT VOLTAGE SUPPRESSOR (TVS) AND EMI FILTER
A vertical TVS (VTVS) circuit includes a semiconductor substrate for supporting the VTVS device thereon having a heavily doped layer extending to the bottom of...
2017/0373157 Power Semiconductor Device
A power semiconductor device has a semiconductor body configured to conduct a load current in parallel to an extension direction between first and second load...
2017/0373156 P-DOPING OF GROUP-III-NITRIDE BUFFER LAYER STRUCTURE ON A HETEROSUBSTRATE
An epitaxial group-ill-nitride buffer-layer structure is provided on a heterosubstrate, wherein the buffer-layer structure has at least one stress-management...
2017/0373155 SUBSTRATE FOR SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE USING THE SAME
The present invention provides a substrate for a semiconductor device and a semiconductor device using the same. The substrate for a semiconductor device...
2017/0373154 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device includes: an n- type layer disposed on a first surface of an n+ type silicon carbide substrate; a first trench formed in the n- type...
2017/0373153 SYNTHESIS AND PROCESSING OF PURE AND NV NANODIAMONDS AND OTHER NANOSTRUCTURES FOR QUANTUM COMPUTING AND...
Using processes disclosed herein, materials and structures are created and used. For example, processes can include melting amorphous carbon doped with...
2017/0373152 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
The present techniques relate to a semiconductor device having resistance which has a positive temperature coefficient and a suitable value, and to a method...
2017/0373151 SEMICONDUCTOR DEVICE HAVING IMPURITY REGION
A semiconductor device having an impurity region is provided. The semiconductor device includes a fin active region having protruding regions and a recessed...
2017/0373150 STRAINED SEMICONDUCTOR DEVICE
A semiconductor device comprises a first semiconductor fin having a first width, the first semiconductor fin is arranged on a first portion of the strain...
2017/0373149 III-V EXTENSION BY HIGH TEMPERATURE PLASMA DOPING
A method for forming an overlap transistor includes forming a gate structure over a III-V material, wet cleaning the III-V material on side regions adjacent to...
2017/0373148 ASYMMETRIC FET
After forming a first-side epitaxial semiconductor region and a second-side epitaxial semiconductor region on recessed surfaces of a semiconductor portion that...
2017/0373147 SELECTIVE GERMANIUM P-CONTACT METALIZATION THROUGH TRENCH
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be...
2017/0373146 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device including a well resistance element of high accuracy and high withstand voltage and a method of manufacturing the semiconductor device...
2017/0373145 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
In an SOI substrate having a semiconductor substrate serving as a support substrate, an insulating layer on the semiconductor substrate and a semiconductor...
2017/0373144 NOVEL STI PROCESS FOR SDB DEVICES
A shallow trench isolation (STI) structure is formed having a conventional STI trench structure formed of dielectric material extending into the substrate. A...
2017/0373143 METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE
A method of manufacturing a semiconductor structure includes the following steps. A first raised portion is formed on a semiconductor substrate. The height of...
2017/0373142 SEMICONDUCTOR DEVICE HAVING SIDE-DIFFUSED TRENCH PLUG
A semiconductor device structure may include a substrate having a substrate base comprising a first dopant type; a semiconductor layer disposed on a surface of...
2017/0373141 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
A method of manufacturing a semiconductor device having an insulated gate bipolar transistor portion and a freewheeling diode portion. The method includes...
2017/0373140 Semiconductor Device with Field Dielectric in an Edge Area
A semiconductor device includes a semiconductor body with transistor cells arranged in an active area and absent in an edge area between the active area and a...
2017/0373139 POWER TRENCH MOSFET WITH IMPROVED UNCLAMPED INDUCTIVE SWITCHING (UIS) PERFORMANCE AND PREPARATION METHOD THEREOF
A trench type power semiconductor device with improved breakdown voltage and UIS performance and a method for preparation the device are disclosed. The trench...
2017/0373138 Semiconductor Device Including an LDMOS Transistor and a Resurf Structure
In an embodiment, a high frequency amplifying circuit includes a semiconductor device. The semiconductor device includes a semiconductor substrate having a...
2017/0373137 SEMICONDUCTOR DEVICE INCLUDING A LDMOS TRANSISTOR
In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity .rho..gtoreq.100 Ohm.cm, a front surface and a rear...
2017/0373136 Integrated Circuit Devices Having Features With Reduced Edge Curvature and Methods for Manufacturing the Same
A structure such as an integrated circuit device is described having a line of material with critical dimensions which vary within a distribution substantially...
2017/0373135 SEMICONDUCTOR DEVICE
A highly reliable semiconductor device including, an oxide semiconductor is provided. Provided is a semiconductor device including an oxide semiconductor...
2017/0373134 2D Material Super Capacitors
Devices and methods are described relating to capacitor energy storage devices that are small in size and have a high energy stored to volume ratio. The...
2017/0373133 MAGNETIC CORE INDUCTORS FOR INTEGRATED VOLTAGE REGULATOR
A device includes an insulating layer disposed over a silicon substrate. The insulating layer includes a core insulating area and a peripheral insulating area....
2017/0373132 ORGANIC LIGHT-EMITTING DISPLAY DEVICE
An organic light-emitting display device includes a substrate including a display area and a peripheral area surrounding the display area. The display area...
2017/0373131 ORGANIC ELECTROLUMINESCENT LIGHT EMITTING DISPLAY DEVICE
In an organic electroluminescent light emitting display device comprising a plurality of pixels each of which includes an organic electroluminescent element...
2017/0373130 ORGANIC LIGHT-EMITTING DISPLAY APPARATUS INCLUDING MULTILAYER AUXILIARY ELECTRODE AND METHOD OF MANUFACTURING...
A method of manufacturing an organic light-emitting display apparatus includes: forming an auxiliary electrode including: a first conductive layer; and a...
2017/0373129 ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING AN ORGANIC LIGHT EMITTING DISPLAY DEVICE
An organic light emitting display (OLED) device includes a substrate comprising a display region and a peripheral region. The OLED device further includes a...
2017/0373128 DISPLAY APPARATUS
A display apparatus includes a substrate, a display unit over the substrate, the display unit including a thin film transistor, a display element connected to...
2017/0373127 DISPLAY UNIT AND ELECTRONIC APPARATUS
A display unit includes a light emitting layer including a light emitting device; a color filter layer including a color filter corresponding to the light...
2017/0373126 DISPLAY APPARATUS
Disclosed herein is a display apparatus, including, a panel having a plurality of pixels disposed in a matrix and each including a self-luminous element for...
2017/0373125 FLEXIBLE DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME
A flexible display device includes: a panel portion including a display area and a pad area; a window disposed over the panel; an adhesive layer disposed...
2017/0373124 Electroluminescence Display Device
Embodiments disclosed herein relate to an electroluminescence display device including a first electrode, a second electrode facing the first electrode, an...
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