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| Patent # | Description |
|---|---|
| 2017/0373072 |
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE A semiconductor device can be reduced in size. The semiconductor device has a first conductivity type p type well layer extending in the X direction of the... |
| 2017/0373071 |
VERTICAL CHANNEL TRANSISTOR-BASED SEMICONDUCTOR STRUCTURE A semiconductor memory structure includes adjacent cross-sectionally rectangular-shaped bottom source and drain electrodes, the electrodes including n-type... |
| 2017/0373070 |
MIRROR CONTACT CAPACITOR A semiconductor structure and a method for fabricating the same. The semiconductor structure includes a substrate and a bonding layer in contact with a top... |
| 2017/0373069 |
SEMICONDUCTOR DEVICE COMPRISING GATE STRUCTURE SIDEWALLS HAVING DIFFERENT
ANGLES The present disclosure provides a semiconductor device including a substrate, a first active region, a second active region, and a gate structure. The first... |
| 2017/0373068 |
SEMICONDUCTOR MEMORY DEVICE The memory capacity of a DRAM is enhanced. A semiconductor memory device includes a driver circuit including part of a single crystal semiconductor substrate,... |
| 2017/0373067 |
SEMICONDUCTOR DEVICE A semiconductor device capable of retaining data for a long time is provided. A leakage current path between adjacent memory cells in a memory cell array... |
| 2017/0373066 |
Method and Structure for FinFET Device The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with... |
| 2017/0373065 |
SEMICONDUCTOR DEVICE The semiconductor device includes a first inverter and a second inverter which is connected thereto in series. Each of the first and the second inverters... |
| 2017/0373064 |
HETEROGENEOUSLY INTEGRATED SEMICONDUCTOR DEVICE AND MANUCACTURING METHOD
THEREOF A heterogeneously integrated semiconductor devices includes a base substrate; a Ge-containing film formed on the base substrate; a PMOSFET transistor having a... |
| 2017/0373063 |
FORMATION OF A SEMICONDUCTOR DEVICE WITH SELECTIVE NITRIDE GROWN ON
CONDUCTOR A method of forming a fin-type field effect transistor (FinFET) according to one or more embodiments comprise etching a gate spacer of a complementary pair of... |
| 2017/0373062 |
Semiconductor Device and Method for Fabricating the Same The semiconductor device includes a first multi-channel active pattern protruding from a substrate, and having a first height, a second multi-channel active... |
| 2017/0373061 |
SIMULTANEOUSLY FABRICATING A HIGH VOLTAGE TRANSISTOR AND A FINFET Forming a semiconductor layer on a semiconductor substrate, a top surface of the semiconductor layer above a fin in a second region is higher than a top... |
| 2017/0373060 |
DEVICE FOR A FINFET A semiconductor device includes a semiconductor substrate, multiple fins formed on a front surface of the semiconductor substrate, a stress layer formed on a... |
| 2017/0373059 |
FINFET AND MANUFACTURING METHOD OF THE SAME A FinFET that includes a semiconductor substrate that has insulating areas, a fin structure, a gate dielectric layer, a gate electrode structure, a drain... |
| 2017/0373058 |
METHODS OF GATE REPLACEMENT IN SEMICONDUCTOR DEVICES A method of forming a semiconductor device includes forming a plurality of fins on a substrate, forming a polysilicon gate structure, and replacing the... |
| 2017/0373057 |
ARRAY SUBSTRATE AND MANUFACTURING METHOD FOR THE SAME A manufacturing method for an array substrate is disclosed. The method includes: forming a gate electrode on a substrate; depositing a gate insulation layer, a... |
| 2017/0373056 |
Vertical Metal Insulator Metal Capacitor Having a High-K Dielectric
Material A vertical metal-insulator-metal (MIM) capacitor is formed within multiple layers of a multi-level metal interconnect system of a chip. The vertical MIM... |
| 2017/0373055 |
SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD OF THE SAME In a non-insulated DC-DC converter having a circuit in which a power MOS.cndot.FET high-side switch and a power MOS.cndot.FET low-side switch are connected in... |
| 2017/0373054 |
SEMICONDUCTOR SWITCH DEVICE A semiconductor switch device and a method of making the same. The semiconductor switch device includes a field effect transistor located on a semiconductor... |
| 2017/0373053 |
ESD PROTECTION STRUCTURE An ESD protection structure formed within a semiconductor substrate of an integrated circuit device. The ESD protection structure comprises a thyristor... |
| 2017/0373052 |
FABRICATION OF RADIO-FREQUENCY DEVICES WITH AMPLIFIER VOLTAGE LIMITING
FEATURES Fabrication of a wireless device involves providing a packaging substrate configured to receive a plurality of components, mounting a radio-frequency module on... |
| 2017/0373051 |
Method of Manufacturing a Package-on-Package Type Semiconductor Package A method for manufacturing a semiconductor package, for example a package-on-package type semiconductor device package. As non-limiting examples, various... |
| 2017/0373050 |
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE THEREOF Semiconductor devices and methods of manufacture thereof are disclosed. In some embodiments, a method of manufacturing a device includes coupling a first... |
| 2017/0373049 |
LED MODULE The invention relates to an LED module with a circuit which comprises an LED (106) and a resonant circuit (106, 108, 110) for coupling in energy for operation... |
| 2017/0373048 |
Multi-Die Structure and Method for Forming Same A device includes a semiconductor structure comprising a top package stacked on a bottom package, wherein the bottom package comprises a plurality of bottom... |
| 2017/0373047 |
LIGHT EMITTING DEVICE A light emitting device includes a substrate, a plurality of micro light emitting chips and a plurality of conductive bumps. The substrate has a plurality of... |
| 2017/0373046 |
LIGHT EMITTING DIODE ARRAY ON A BACKPLANE AND METHOD OF MAKING THEREOF A backplane optionally having stepped horizontal surfaces and optionally embedding metal interconnect structures is provided. First conductive bonding... |
| 2017/0373045 |
LIGHT EMITTER COMPONENTS AND RELATED METHODS Light emitter components and related methods are provided. In some aspects, light emitter components and related methods include a ceramic submount having a... |
| 2017/0373044 |
INTERCONNECT STRUCTURES AND SEMICONDUCTOR STRUCTURES FOR ASSEMBLY OF
CRYOGENIC ELECTRONIC PACKAGES A cryogenic electronic package includes at least two superconducting and/or conventional metal semiconductor structures. Each of the semiconductor structures... |
| 2017/0373043 |
INTERCONNECTION STRUCTURES AND METHODS FOR MAKING THE SAME The present disclosure provides a method for interconnecting components. First and second substrates are provided. First and second components are respectively... |
| 2017/0373042 |
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF A semiconductor device includes n semiconductor chips stacked via electrical contacting means in the silicon substrate thickness direction, n being an integer... |
| 2017/0373041 |
METHOD OF MANUFACTURING WAFER LEVEL PACKAGE AND WAFER LEVEL PACKAGE
MANUFACTURED THEREBY Provided are a wafer level package and a manufacturing method thereof. A reconfigured substrate may be formed by disposing a first semiconductor die on a dummy... |
| 2017/0373040 |
SEMICONDUCTOR ELECTRONIC DEVICE WITH IMPROVED TESTING FEATURES AND
CORRESPONDING PACKAGING METHOD An electronic device provided with a package housing a stacked structure formed by dies of semiconductor material, which have a respective integrated circuit... |
| 2017/0373039 |
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD OF THE SAME The present disclosure provides a semiconductor including a first semiconductor die layer having an active surface, a conductive contact electrically coupled... |
| 2017/0373038 |
SEMICONDUCTOR PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME A semiconductor package structure has a first electronic component on an insulating layer, a dielectric layer on the insulating layer and surrounding the first... |
| 2017/0373037 |
INTEGRATED FAN-OUT PACKAGE AND METHOD FOR FABRICATING THE SAME An integrated fan-out package including an integrated circuit, a plurality of memory devices, an insulating encapsulation, and a redistribution circuit... |
| 2017/0373036 |
DISPLAY DEVICE AND DRIVING METHOD OF DISPLAY DEVICE A display device includes first and second display elements, first to fourth transistors, and a first insulating layer. The first insulating layer is... |
| 2017/0373035 |
FAN-OUT SEMICONDUCTOR PACKAGE MODULE A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a ... |
| 2017/0373034 |
TIN-INDIUM BASED LOW TEMPERATURE SOLDER ALLOY A lead-free solder alloy having a low melting temperature and low yield strength is disclosed. The solder alloy includes 5.0-20.0 wt. % of indium (In), 1.0-5.0... |
| 2017/0373033 |
DEFORMABLE CONDUCTIVE CONTACTS Deformable conductive contacts are provided. A plurality of deformable contacts on a first substrate may be joined to a plurality of conductive pads on a... |
| 2017/0373031 |
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME The semiconductor device includes: a semiconductor substrate; a conductor layer formed over the semiconductor substrate and having an upper surface and a lower... |
| 2017/0373030 |
FAN-OUT SEMICONDUCTOR PACKAGE A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first... |
| 2017/0373029 |
FAN-OUT SEMICONDUCTOR PACKAGE A fan-out semiconductor package includes a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole of the first... |
| 2017/0373028 |
DISPLAY APPARATUS A display apparatus is provided. The display apparatus includes a display substrate and a plurality of pads arranged above the display substrate. Each of the... |
| 2017/0373027 |
FAN-OUT SEMICONDUCTOR PACKAGE A fan-out semiconductor package includes a semiconductor chip having an active surface, the active surface having a connection pad disposed thereon, and an... |
| 2017/0373026 |
METHOD AND APPARATUS FOR BACK-BIASED SWITCH TRANSISTORS An integrated radio frequency (RF) circuit structure may include an active device on a first surface of an isolation layer. The integrated RF circuit structure... |
| 2017/0373025 |
STACKED SUBSTRATE INDUCTOR In conventional device packages, separate standalone inductors are provided and mounted on an interposer substrate along with a die. Separate inductors reduce... |
| 2017/0373024 |
TAMPER DETECTION FOR A CHIP PACKAGE Chip packages with improved tamper resistance and methods of using such chip packages to provide improved tamper resistance. A lead frame includes a die attach... |
| 2017/0373023 |
PREVENTION OF REVERSE ENGINEERING OF SECURITY CHIPS A semiconductor chip includes a chip substrate; a self-destructive layer arranged on the chip substrate, the self-destructive layer including a pyrophoric... |
| 2017/0373022 |
Forming Large Chips Through Stitching A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first... |
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