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Patent # Description
2017/0373021 SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CHIPS MOUNTED OVER BOTH SURFACES OF SUBSTRATE
A semiconductor chip 10 flip-chip mounted on a first surface 32 of a wiring substrate 30, a semiconductor chip 20 flip-chip mounted on a second surface 33 of...
2017/0373020 RESIN INTERPOSER, SEMICONDUCTOR DEVICE USING RESIN INTERPOSER, AND METHOD OF PRODUCING RESIN INTERPOSER
A resin interposer having a semiconductor chip mounted thereon to couple the semiconductor chip to a printed circuit board, the resin interposer includes a...
2017/0373019 METHOD TO MITIGATE CHIP PACKAGE INTERACTION RISK ON DIE CORNER USING REINFORCING TILES
A method for producing semiconductor devices including reinforcing metal tiles and the resulting semiconductor package are provided. Embodiments include...
2017/0373018 IMAGE PICKUP APPARATUS AND CAMERA MODULE
An image pickup apparatus includes an optical device, a transparent conductive film, an electrode pad, and a penetrating electrode. In the optical device, an...
2017/0373017 HIGH FREQUENCY SEMICONDUCTOR DEVICE AND PACKAGE THEREFOR
A high frequency semiconductor device package includes a metal plate, a frame body, a first lead part, a second lead part, a first conductive layer, and a...
2017/0373016 PACKAGED SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING A PACKAGED SEMICONDUCTOR DEVICE
In accordance with some embodiments of the present disclosure, a packaged semiconductor device includes a first package structure, at least one outer...
2017/0373015 SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND GENERATION METHOD OF UNIQUE INFORMATION
A semiconductor device with improved generation function of unique information is provided. The semiconductor device includes an integrated circuit designed or...
2017/0373014 DISPLAY DEVICE AND ACTIVE ELEMENT SUBSTRATE
A display device is provided. The display device includes a first substrate, a second substrate, a display layer, an active element layer, and a planar layer...
2017/0373013 SURFACE TREATMENT FOR SEMICONDUCTOR STRUCTURE
A method includes forming a dielectric layer and forming a metallic conductor at least partially in the dielectric layer. Formation of the metallic conductor...
2017/0373012 SEMICONDUCTOR PACKAGE AND METHOD FOR PRODUCING SAME
An object of the present invention is to provide a semiconductor package with which it is possible to reduce a volume of an encapsulation resin and to easily...
2017/0373011 SEMICONDUCTOR DIE BACKSIDE DEVICES AND METHODS OF FABRICATION THEREOF
A die for a semiconductor chip package includes a first surface including an integrated circuit formed therein. The die also includes a backside surface...
2017/0373010 PACKAGE-ON-PACKAGE TYPE SEMICONDUCTOR DEVICE INCLUDING FAN-OUT MEMORY PACKAGE
A semiconductor device may include a bottom package embedded with a first semiconductor chip. The semiconductor device may include a middle package stacked...
2017/0373009 ELECTRONIC COMPONENT
An electronic component includes a first electronic component and a second electronic component that is stacked on the first electronic component. A second...
2017/0373008 ISOLATION BETWEEN SEMICONDUCTOR COMPONENTS
In some general aspects, an apparatus may include a first semiconductor die, a second semiconductor die, and a capacitive isolation circuit being coupled to...
2017/0373007 CONTACT LINE HAVING INSULATING SPACER THEREIN AND METHOD OF FORMING SAME
One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a contact line being disposed within a...
2017/0373006 BICONVEX LOW RESISTANCE METAL WIRE
At least one opening having a biconvex shape is formed into a dielectric material layer. A void-free metallization region (interconnect metallic region and/or...
2017/0373005 ANTI-FUSES WITH REDUCED PROGRAMMING VOLTAGES
Device structures for an anti-fuse and methods for manufacturing device structures for an anti-fuse. The anti-fuse includes a first terminal comprised of a...
2017/0373004 Wireless Charging Package with Chip Integrated in Coil Center
A package includes a device die, and an encapsulating material encapsulating the device die therein. The encapsulating material has a top surface coplanar with...
2017/0373003 SEMICONDUCTOR CHIP AND MULTI-CHIP PACKAGE USING THEREOF
The present disclosure provides a semiconductor chip having a non-through plug contour (buried alignment mark) for stacking aligmnent and a multi-chip...
2017/0373002 Semiconductor Device and Method Fabricating the Same
According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes a first seal ring and a first circuit. The first...
2017/0373001 LOW-DISPERSION COMPONENT IN AN ELECTRONIC CHIP
A method of manufacturing electronic chips containing low-dispersion components, including the steps of: mapping the average dispersion of said components...
2017/0373000 INTERCONNECTS HAVING HYBRID METALLIZATION
Disclosed are methods of forming integrated circuit (IC) structures with hybrid metallization interconnects. A dual damascene process is performed to form...
2017/0372999 CONDUCTIVE TERMINAL ON INTEGRATED CIRCUIT
A conductive terminal on an integrated circuit is provided. The conductive terminal includes a conductive pad, a dielectric layer, and a conductive via. The...
2017/0372998 SHEET MOLDING PROCESS FOR WAFER LEVEL PACKAGING
Discussed generally herein are methods and devices including or providing a redistribution layer device without under ball metallization. A device can include...
2017/0372997 WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE
A wiring substrate includes a first insulating layer including a first through-hole formed through the first insulating layer in a thickness direction, a...
2017/0372996 SEMICONDUCTOR DEVICE
A bonding pad of a semiconductor chip in a QFP includes, in its exposed portion, a via disposition area comprising: a first segment that connects a corner and...
2017/0372995 FAN-OUT SEMICONDUCTOR PACKAGE
A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by...
2017/0372994 POROUS ALUMINA TEMPLATES FOR ELECTRONIC PACKAGES
Interposers and methods of making the same are disclosed herein. In one embodiment, an interposer includes a region having first and second oppositely facing...
2017/0372993 SUBSTRATE INTERMEDIARY BODY, THROUGH-HOLE VIA ELECTRODE SUBSTRATE, AND THROUGH-HOLE VIA ELECTRODE FORMATION METHOD
A substrate intermediary body includes: a substrate having a hole in a thickness direction, and a conductor being disposed in the hole; and an adhesion layer...
2017/0372992 FILM PRODUCT, FILM PACKAGES AND PACKAGE MODULES USING THE SAME
In an embodiment, the film product includes a film substrate having a first surface and a second surface opposite the first surface. The film substrate has a...
2017/0372991 WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE
A wiring substrate includes a first wiring layer, an insulative resin first insulation layer covering the first wiring layer, and a second wiring layer located...
2017/0372990 SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor element, a circuit board, metal wires, and an expanding member. The circuit board has an upper surface and a...
2017/0372989 EXPOSED SIDE-WALL AND LGA ASSEMBLY
A device package with a reduced foot print may include a substrate and a through-substrate via extending from a top surface to a bottom surface of the...
2017/0372988 WAFER LEVEL CHIP SCALE SEMICONDUCTOR PACKAGE
This disclosure relates to a method of forming a wafer level chip scale semiconductor package, the method comprising: providing a carrier having a cavity...
2017/0372987 SEMICONDUCTOR POWER DEVICE HAVING SINGLE IN-LINE LEAD MODULE AND METHOD OF MAKING THE SAME
A semiconductor power device is disclosed. The semiconductor power device comprises a lead frame unit, two or more pluralities of single in-line leads, two or...
2017/0372986 LDMOS Transistor and Method
In an embodiment, a semiconductor device includes a semiconductor substrate, a LDMOS transistor arranged in a front surface of the semiconductor substrate and...
2017/0372985 LDMOS Transistor and Method
In an embodiment, a semiconductor device includes a semiconductor substrate having a front surface, a LDMOS transistor arranged in the front surface of the...
2017/0372984 Systems and Methods for Thermal Conduction Using S-Contacts
An integrated circuit architecture that provides a path having relatively low thermal resistance between one or more electronic devices and one or more thermal...
2017/0372983 Thermally Conductive and Electrically Isolating Layers in Semiconductor Structures
A semiconductor structure includes a semiconductor wafer having at least one semiconductor device integrated in a first device layer, a thermally conductive...
2017/0372982 Integration of Thermally Conductive but Electrically Isolating Layers with Semiconductor Devices
A semiconductor structure includes a semiconductor wafer having at least one semiconductor device integrated in a first device layer, a thermally conductive...
2017/0372981 FAN-OUT WAFER LEVEL PACKAGE STRUCTURE
A fan-out wafer level package structure includes a chip, a molding compound, at least one circuit layer, and at least one dielectric layer. The molding...
2017/0372980 METHOD FOR MANUFACTURING WIRING BOARD
A method for manufacturing a wiring board includes forming on a first support plate a first laminated wiring portion including conductor and insulating layers...
2017/0372979 STACKED SILICON PACKAGE ASSEMBLY HAVING CONFORMAL LID
A chip package assembly and method for fabricating the same are provided which utilize a conformal lid to improve the chip package assembly from deformation....
2017/0372978 SEMICONDUCTOR DEVICE
A relay substrate in which a circuit pattern and an external electrode are integrated on a insulating plate is used in the semiconductor device. Such...
2017/0372977 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME
A semiconductor device has a U terminal with an internal joint portion at one end that is joined to a circuit board, an intermediate portion that is embedded...
2017/0372976 Packaging Mechanisms for Dies with Different Sizes of Connectors
Embodiments of mechanisms for testing a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical...
2017/0372975 INLINE KERF PROBING OF PASSIVE DEVICES
A radio frequency (RF) integrated circuit may include a die having passive components including at least one pair of capacitors covered by a first dielectric...
2017/0372974 Method and Structure for Mandrel and Spacer Patterning
An IC manufacturing method includes forming first mandrels and second mandrels over a substrate; and forming first spacers on sidewalls of the first mandrels...
2017/0372973 SIDEWALL IMAGE TRANSFER STRUCTURES
A semiconductor device comprises a source/drain region arranged on a substrate and a first gate stack having a first length arranged on a first channel region...
2017/0372972 ELECTRONIC CIRCUIT DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC CIRCUIT DEVICE
An electronic circuit device includes a plurality of logic circuit elements which output an output signal by performing a preset operation on an input signal....
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