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Patent # Description
2017/0372971 Integrated Circuit Devices
An integrated circuit device may include a gate insulation layer covering a top surface and opposite sidewalls of a fin-shaped active region, a gate electrode...
2017/0372970 FORMING INSULATOR FIN STRUCTURE IN ISOLATION REGION TO SUPPORT GATE STRUCTURES
A method for forming the semiconductor device that includes forming a plurality of composite fin structures across a semiconductor substrate including an...
2017/0372969 System and Method for Widening Fin Widths for Small Pitch FinFET Devices
A FinFET includes a semiconductor layer having a fin structure that protrudes out of the semiconductor layer. The fin structure includes a first segment and a...
2017/0372968 FIN PITCH SCALING FOR HIGH VOLTAGE DEVICES AND LOW VOLTAGE DEVICES ON THE SAME WAFER
A semiconductor device is provided that includes a first plurality of fin structures having a first width in a first region of a substrate, and a second...
2017/0372967 Process for fabricating a transistor structure including a plugging step
A process for fabricating a transistor structure produced sequentially, comprises at least one string of the following steps: producing at least one first...
2017/0372966 Semiconductor Layer Separation from Single Crystal Silicon Substrate by Infrared Irradiation of Porous Silicon...
Methods and equipment for the removal of semiconductor wafers grown on the top surface of a single crystal silicon substrate covered by a porous silicon...
2017/0372965 METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING COMBINED...
A method for manufacturing a semiconductor substrate according to the present invention includes preparing a seed substrate containing a semiconductor...
2017/0372964 SEMICONDUCTOR DEVICE AND METHOD COMPRISING REDISTRIBUTION LAYERS
A method of making a semiconductor package can include placing a single layer dielectric film on a temporary carrier substrate. A plurality of semiconductor...
2017/0372963 WAFER PARTITIONING METHOD AND DEVICE FORMED
A method of partitioning a wafer includes defining a scribe line surrounding a set of dies. The method further includes etching a plurality of trenches into...
2017/0372962 SEMICONDUCTOR DIE SINGULATION METHODS
Methods of singulating semiconductor die. Specific implementations may include: providing a semiconductor wafer including a plurality of die located on a first...
2017/0372961 VIAS AND CONDUCTIVE ROUTING LAYERS IN SEMICONDUCTOR SUBSTRATES
Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a...
2017/0372960 SELF-ALIGNED INTERCONNECTS FORMED USING SUBTRACTIVE TECHNIQUES
A method of forming an interconnect structure for semiconductor or MEMS structures at a 10 nm Node (16 nm HPCD) down to 5 nm Node (7 nm HPCD), or lower, where...
2017/0372959 GATE TIE-DOWN ENABLEMENT WITH INNER SPACER
A method for forming a gate tie-down includes opening up a cap layer and recessing gate spacers on a gate structure to expose a gate conductor; forming inner...
2017/0372958 FILM-EDGE TOP ELECTRODE
In one example, an electronic device includes a layer of insulator on a substrate extending to a set of device elements. A first set of metal layers having a...
2017/0372957 SELF-ALIGNED CONTACT
A method for fabricating self-aligned contacts includes forming a liner over a gate structure having a gate conductor and one sidewall spacer and etching an...
2017/0372956 SELF-ALIGNED CONTACT
A semiconductor device includes a gate structure having a gate conductor and a sidewall spacer. A partial dielectric cap is formed on the gate conductor and...
2017/0372955 PROCESS OF FORMING SEMICONDUCTOR DEVICE HAVING INTERCONNECTION FORMED BY ELECTRO-PLATING
A process of forming a semiconductor device that includes an interconnection formed by electro-plating is disclosed. The process comprises steps of: forming a...
2017/0372954 REFLOW ENHANCEMENT LAYER FOR METALLIZATION STRUCTURES
A reflow enhancement layer is formed in an opening prior to forming and reflowing a contact metal or metal alloy. The reflow enhancement layer facilitates the...
2017/0372953 CVD BASED OXIDE-METAL MULTI STRUCTURE FOR 3D NAND MEMORY DEVICES
Implementations described herein generally relate to a method for forming a metal layer and to a method for forming an oxide layer on the metal layer. In one...
2017/0372952 SUBSTRATE AND METHOD INCLUDING FORMING A VIA COMPRISING A CONDUCTIVE LINER LAYER AND CONDUCTIVE PLUG HAVING...
In an embodiment, a substrate includes semiconductor material and a conductive via. The conductive via includes a via in the substrate, a conductive plug...
2017/0372951 METHOD AND PROCESSING APPARATUS FOR PERFORMING PRE-TREATMENT TO FORM COPPER WIRING IN RECESS FORMED IN SUBSTRATE
There is provided a method for performing a pre-treatment to form a copper wiring in a recess formed in a substrate, which includes forming a barrier layer on...
2017/0372950 INTERCONNECT WIRES INCLUDING RELATIVELY LOW RESISTIVITY CORES
A dielectric layer and a method of forming thereof. An opening defined in a dielectric layer and a wire deposited within the opening, wherein the wire includes...
2017/0372949 TITANIUM SILICIDE FORMATION IN A NARROW SOURCE-DRAIN CONTACT
Aspects of the present invention relate to approaches for forming a narrow source-drain contact in a semiconductor device. A contact trench can be etched to a...
2017/0372948 Interconnect Structure and Method
A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert...
2017/0372947 CONFORMAL LOW TEMPERATURE HERMETIC DIELECTRIC DIFFUSION BARRIERS
Conformal hermetic dielectric films suitable as dielectric diffusion barriers over 3D topography. In embodiments, the dielectric diffusion barrier includes a...
2017/0372946 HIGH RESISTIVITY SILICON-ON-INSULATOR SUBSTRATE COMPRISING AN ISOLATION REGION
A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a...
2017/0372945 Reduced Substrate Effects in Monolithically Integrated RF Circuits
A method of forming a semiconductor structure is disclosed. The method includes forming a semiconductor wafer having a device layer situated over a handle...
2017/0372944 METHODS FOR FABRICATING TRENCH ISOLATION STRUCTURE
A method for fabricating a trench isolation structure is provided. The method includes providing a substrate and forming a patterned mask layer on the...
2017/0372943 Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect...
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
2017/0372942 Methods of Forming One or More Covered Voids in a Semiconductor Substrate, Methods of Forming Field Effect...
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
2017/0372941 Methods Of Forming One Or More Covered Voids In A Semiconductor Substrate
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
2017/0372940 Methods Of Forming One Or More Covered Voids In A Semiconductor Substrate
Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for...
2017/0372939 SENSOR ARRAY WITH ANTI-DIFFUSION REGION(S) TO EXTEND SHELF LIFE
The inventive concepts disclosed herein are generally directed to a sensor array device that has a prolonged shelf life but requires only a minimal amount of...
2017/0372938 WORKPIECE LOADER FOR A WET PROCESSING SYSTEM
Techniques herein provide a workpiece handling and loading apparatus for loading, unloading, and handling relatively flexible and thin substrates for transport...
2017/0372937 WORKPIECE HOLDER FOR A WET PROCESSING SYSTEM
Techniques herein provide a workpiece holder that can hold relatively flexible and thin workpieces for transport and electrochemical deposition while avoiding...
2017/0372936 THERMOSETTING ADHESIVE SHEET AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
A thermosetting adhesive sheet and a method for manufacturing a semiconductor device capable of reducing warping of a semiconductor wafer are provided. The...
2017/0372935 METHOD OF COLLECTIVE FABRICATION OF 3D ELECTRONIC MODULES CONFIGURED TO OPERATE AT MORE THAN 1 GHZ
A method of collective fabrication of 3D electronic modules, each 3D electronic module comprising a stack of at least two, surface transferable, ball grid...
2017/0372934 WAFER HOLDING APPARATUS AND BASEPLATE STRUCTURE
A wafer holding apparatus includes an electrostatic chuck configured to clamp an object, a baseplate made of aluminum and configured to support the...
2017/0372932 INTEGRATED CHIP DIE CARRIER EXCHANGER
The present disclosure relates to an integrated chip (IC) processing tool having a die exchanger configured to automatically transfer a plurality of IC die...
2017/0372931 HORIZONTAL SUBSTRATE CONTAINER WITH INTEGRAL CORNER SPRING FOR SUBSTRATE CONTAINMENT
A substrate container including substrate supports, such as concentric rings, adapted to receive substrates in a substrate stack. The container includes a base...
2017/0372930 Substrate Storage and Processing
The system, method and apparatus described relates generally to a device related to substrate storage and processing. In one example embodiment to methods,...
2017/0372929 MULTIPLE GASES PROVIDING METHOD AND MULTIPLE GASES PROVIDING APPARATUS
Provided is a method for multi-supplying gas, the method comprising: installing a control valve and an flow meter on each of a plurality of branch lines...
2017/0372928 SUBSTRATE PROCESSING SYSTEM AND TEMPERATURE CONTROL METHOD
Disclosed is a substrate processing system including a substrate processing apparatus; and a control device that controls the substrate processing apparatus....
2017/0372927 DIODES OFFERING ASYMMETRIC STABILITY DURING FLUIDIC ASSEMBLY
Embodiments are related to systems and methods for fluidic assembly, and more particularly to systems and methods for assuring deposition of elements in...
2017/0372926 SUBSTRATE TREATING UNIT, BAKING APPARATUS INCLUDING THE SAME, AND SUBSTRATE TREATING METHOD USING BAKING APPARATUS
Disclosed is a heating unit that heats a substrate. The heating unit includes a housing providing a treatment space in the interior thereof, a heating plate...
2017/0372925 SYSTEM AND RELATED TECHNIQUES FOR HANDLING ALIGNED SUBSTRATE PAIRS
An industrial-scale system and method for handling precisely aligned and centered semiconductor substrate (e.g., wafer) pairs for substrate-to-substrate (e.g.,...
2017/0372924 SELF-CONTAINED METROLOGY WAFER CARRIER SYSTEMS
A self-contained metrology wafer carrier systems and methods of measuring one or more characteristics of semiconductor wafers are provided. A wafer carrier...
2017/0372923 FLOW PASSAGE STRUCTURE, INTAKE AND EXHAUST MEMBER, AND PROCESSING APPARATUS
A flow passage structure includes a member. The member includes a plurality of first openings, a plurality of second openings, a flow passage, and a plurality...
2017/0372922 APPARATUS AND METHOD FOR TREATING SUBSTRATE
Provided is a substrate treating apparatus. The substrate treating apparatus comprises: a support unit provided to support the substrate and rotate the...
2017/0372921 SUBSTRATE TREATING METHOD
An upper end of a tubular member surrounding a common pipe line is closed by a lid member. The lid member has an opening formed therein for supplying liquids...
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