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Patent # Description
2017/0371857 HYBRID APPROACH FOR SHORT FORM DETECTION AND EXPANSION TO LONG FORMS
Embodiments provide a system and method for short form and long form detection. Given candidate short forms, the system can generate one or more n-gram...
2017/0371856 PERSONALIZED SUMMARY GENERATION OF DATA VISUALIZATIONS
Various embodiments are generally directed to systems for summarizing data visualizations (i.e., images of data visualizations), such as a graph image, for...
2017/0371855 COLLECTING AND AUDITING STRUCTURED DATA LAYERED ON UNSTRUCTURED OBJECTS
Various embodiments relating to collecting and auditing structured data layered on unstructured object are disclosed. In one embodiment, a field-data tracking...
2017/0371854 CONSISTENT RESOURCE MANAGEMENT AND VERSION MANAGEMENT SERVICE BASED ON FORMAL CERTIFICATION
A Version management Service (VMS) that enables consistent management of dynamic digital resources throughout their life cycle. The service handles the...
2017/0371853 MEASUREMENT OF VISIBILITY OF OVERLAY CONTENT
Systems and methods of measuring the visibility of overlay content in a display of a computing device are provided. A page renderer can identify a position of...
2017/0371852 SYSTEM AND METHOD FOR IN-BROWSER EDITING
The present invention relates to an in-browser editor. Specifically, embodiments of the present invention provide a system and method of editing content in a...
2017/0371851 DETECTING AND ANIMATING A CHANGE IN POSITION OF A VISUAL LAYOUT NODE OF A VISUAL LAYOUT TREE
A layout engine generates a visual layout tree for a visual description tree of a document whose content is to be rendered in one or more display areas. A...
2017/0371850 PHONETICS-BASED COMPUTER TRANSLITERATION TECHNIQUES
Computer-implemented techniques can include obtaining, by a computer server having one or more processors, a phonetics-based character mapping between a source...
2017/0371849 IN-LINE EDITOR INSERTION
In one example in accordance with the present disclosure, a method for in-line editor insertion includes accessing code for an application that is capable of...
2017/0371848 GENERIC AND AUTOMATED CSS SCOPING
A system and method, including receiving a first file including a first description of a first document presentation for a document in a style sheet language;...
2017/0371847 AUTOTAGGING A TEMPLATE OF A REPORTING WORKBOOK
Autotagging a template of a reporting workbook is provided. The template of the reporting workbook is received. The template is in a first format type. User...
2017/0371846 DOCUMENT SCALE AND POSITION OPTIMIZATION
Methods for optimizing a scale and position of a document in response to a user input is provided are provided. In one aspect, a method includes receiving an...
2017/0371845 Image Preview
A method, apparatus, and system are provided for displaying a graphical representation of at least a portion of a file by interfacing with a graphical...
2017/0371843 INFORMATION PROCESSING APPARATUS, NON-TRANSITORY COMPUTER READABLE MEDIUM, AND INFORMATION PROCESSING METHOD
An information processing apparatus includes an archive file generation unit and a deriving unit. The archive file generation unit generates multiple archive...
2017/0371842 SUPPRESSING PREVIOUSLY CONSUMED CONTENT ITEMS OF A WEBSITE
A browser renders web site views dynamically, based on previously consumed content items. When the browser loads a new web site which contains, among other...
2017/0371841 UNIVERSAL AND AUTOMATED MONTE CARLO METHOD CODE FOR UNCERTAINTY PROPAGATION IN METROLOGY DATABASES
A method of providing transformed target points for integrating a component into an assembly includes collecting a set of component target points, collecting a...
2017/0371840 Digital Sample Rate Conversion
Methods, structures and computer program products for digital sample rate conversion are presented. An input digital sample with a first frequency is converted...
2017/0371839 System And Method For Efficient Sparse Matrix Processing
A system and method for efficient sparse matrix processing are provided in one embodiment. A compressed representation of a sparse matrix, the sparse matrix...
2017/0371838 INFORMATION PROCESSING APPARATUS AND IMAGE PROCESSING METHOD
A processor of an information processing apparatus generates an extended image by adding pixels to outside of a target image. The processor generates an...
2017/0371837 SYSTEMS AND METHODS OF CORRELATING SATELLITE POSITION DATA WITH TERRESTRIAL FEATURES
A method of correlating satellite position data with terrestrial features may include: Using a geometric snapping algorithm to correlate the satellite position...
2017/0371836 METHODS FOR SPECIFYING PROCESSOR ARCHITECTURES FOR PROGRAMMABLE INTEGRATED CIRCUITS
A programmable integrated circuit may include soft and hard logic for implementing a reduced instruction set computing (RISC) processor. Processor generator...
2017/0371835 REMOTE DIRECT MEMORY ACCESS IN A VIRTUALIZED COMPUTING ENVIRONMENT
A method of managing remote direct memory access (RDMA) to a virtual computing instance includes suspending locally initiated RDMA operations of the virtual...
2017/0371834 MEMORY SYSTEM AND METHOD FOR ACCELERATING BOOT TIME
A memory system includes a plurality of memory channels, each of the plurality of memory channels includes a plurality of memory dies and a die processor, each...
2017/0371833 CALCULATOR
A calculator's input interface includes a knob projecting above the top face of the casing. The knob is provided to allow numbers to be input manually. It is...
2017/0371832 METHOD FOR CLOCK SYNCHRONIZATION OF AN INDUSTRIAL INTERNET FIELD BROADBAND BUS
Disclosed is a method for clock synchronization of an industrial internet field broadband bus, wherein the method is applicable to an industrial internet field...
2017/0371831 LOW LATENCY MULTI-PROTOCOL RETIMERS
A multi-protocol retimer apparatus and method for using the same are disclosed. In one embodiment, an apparatus for performing retiming between first and...
2017/0371830 ACCELERATED I3C MASTER STOP
Systems, methods, and apparatus for communication over to serial bus in accordance with an I3C protocol are described. A method performed at a master device...
2017/0371829 EXTERNAL UNIVERSAL BOOSTING AGENT DEVICE
An example system on a chip (SoC) includes a processor, a cache, and a main memory. The processor can receive a data packet from an electronic device via an...
2017/0371828 SYNCHRONOUS INPUT / OUTPUT HARDWARE ACKNOWLEDGEMENT OF WRITE COMPLETIONS
A computer-implemented method for computer-implemented method for communicating completion of synchronous input/output (I/O) commands between a processor...
2017/0371827 Memory with Alternative Command Interfaces
A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support...
2017/0371826 DYNAMIC SYSTEM MANAGEMENT BUS
A dynamic bus communication apparatus for an electrosurgical system includes a data wire, a clock wire, a first variable resistor coupled to the data wire, a...
2017/0371825 Method and Apparatus for Scalable Low Latency Solid State Drive Interface
A solid state drive (SSD) apparatus includes a plurality of solid state drives. The SSD apparatus also includes a channel-interleaved interface operably...
2017/0371824 BUS SHARING SCHEME
A programmable device, having an analog component coupled with an analog bus and a digital component coupled with a digital bus together with a set of 10 pads,...
2017/0371823 BIDIRECTIONAL LANE ROUTING
An apparatus includes a pass-through module that includes connector pins to connect with at least one active motherboard connector and to separately connect...
2017/0371822 PCIE TRAFFIC TRACKING HARDWARE IN A UNIFIED VIRTUAL MEMORY SYSTEM
Techniques are disclosed for tracking memory page accesses in a unified virtual memory system. An access tracking unit detects a memory page access generated...
2017/0371821 DEVICE AND METHOD FOR ALLOWING INTEGRATION OF INCOMPATIBLE DEVICES INTO A VEHICLE BUS NETWORK
A device and method for communication among vehicle components operating on different electronic vehicle bus communication protocols is disclosed. The current...
2017/0371820 In-Connector Data Storage Device
A data storage device includes a case and a connector housed within the case. The connector includes a first connection interface having a plurality of...
2017/0371819 Control method for I2C device of I2C system and I2C device using the same
A control method for a first device of an inter-integrated circuit (I.sup.2C) system including a microcontroller unit (MCU), includes receiving a first...
2017/0371818 METHOD AND APPARATUS FOR DATA DETECTION AND EVENT CAPTURE
One embodiment relates to a data detection and event capture circuit. Data comparator logic receives a monitored data word from a parallel data bus and...
2017/0371817 INTERFACE CIRCUIT RELATING TO VARIABLE DELAY, AND SEMICONDUCTOR APPARATUS AND SYSTEM INCLUDING THE SAME
A semiconductor apparatus may include an interface circuit. The interface circuit may sense level variations of a first signal and a second signal. The...
2017/0371816 INPUT/OUTPUT COMPUTER SYSTEM INCLUDING HARDWARE ASSISTED AUTOPURGE OF CACHE ENTRIES ASSOCIATED WITH PCI ADDRESS...
A computing system includes a processor and a memory unit that stores program instructions. The system purges an entry from an address translation cache in...
2017/0371815 METHOD AND APPARATUS FOR MEMORY ACCESS
Aspects of the disclosure provide an integrated circuit (IC) chip that includes interface circuits and a control circuit. The interface circuits is configured...
2017/0371814 NVME DRIVE DETECTION FROM A SAS/SATA CONNECTOR
Embodiments presented herein provide for hot swappable connections to various storage devices. In one embodiment, a storage controller includes an interface...
2017/0371813 SYNCHRONOUS INPUT/OUTPUT (I/O) CACHE LINE PADDING
A computer-implemented method for synchronous input/output (I/O) cache line padding is described. The cache line padding occurs between a server having a...
2017/0371812 SYSTEM AND METHOD FOR ODD MODULUS MEMORY CHANNEL INTERLEAVING
A system for providing odd modulus memory channel interleaving may include a dynamic random access memory (DRAM) system and a system on chip (SoC). The SoC...
2017/0371811 SYSTEMS AND DEVICES FOR ACCESSING A STATE MACHINE
A device, includes an instruction buffer. The instruction buffer is configured to store instructions related to at least a portion of a data stream to be...
2017/0371810 Data Transmission Method and System
The present application discloses a method and a system for transmitting data. A method embodiment comprises: acquiring a most recent shared memory block index...
2017/0371809 ENCRYPTED MEMORY ACCESS USING PAGE TABLE ATTRIBUTES
Encrypted memory access using page table attributes is disclosed. One example is a memory system including a memory controller at a memory interface. The...
2017/0371808 DIRECT MEMORY ACCESS ENCRYPTION WITH APPLICATION PROVIDED KEYS
In one example in accordance with the present disclosure, a method may include retrieving, at a memory management unit (MMU), encrypted data from a memory via...
2017/0371807 CACHE DATA DETERMINING METHOD AND APPARATUS
The present embodiments provide a cache data determining method and apparatus, and pertain to the field of computer technologies. The method includes:...
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