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Patent # Description
2017/0371806 Pulse Counters
A method and apparatus of a device that reads and writes a plurality of counters is described. In an exemplary embodiment, a device receives plurality labels...
2017/0371805 METHOD AND APPARATUS FOR REDUCING TLB SHOOTDOWN OVERHEADS IN ACCELERATOR-BASED SYSTEMS
A method and apparatus for reducing TLB shootdown operation overheads in accelerator-based computing systems is described. The disclosed method and apparatus...
2017/0371804 Method for Writing Multiple Copies into Storage Device, and Storage Device
A method for writing multiple copies into a storage device includes receiving a first write data request that includes an identity (ID) of a first logical...
2017/0371803 METHOD AND APPARATUS TO ALLOW SECURE GUEST ACCESS TO EXTENDED PAGE TABLES
An apparatus and method for efficient guest EPT manipulation. For example, one embodiment of a apparatus comprises: a hypervisor to create extended page table...
2017/0371802 MICROCONTROLLER FOR MEMORY MANAGEMENT UNIT
One embodiment of the present invention includes a microcontroller coupled to a memory management unit (MMU). The MMU is coupled to a page table included in a...
2017/0371801 INFORMATION PROCESSING APPARATUS AND INFORMATION PROCESSING METHOD
An information processing apparatus includes a memory and a processor coupled to the memory. The memory is configured to store device connection information...
2017/0371800 MEMORY SYSTEM, AND ADDRESS MAPPING METHOD AND ACCESS METHOD THEREOF
Provided is a method for mapping a logical address to a physical address, including: identifying whether a logical address is identical to a round value;...
2017/0371799 MANAGING VIRTUAL-ADDRESS CACHES FOR MULTIPLE MEMORY PAGE SIZES
A translation lookaside buffer stores information indicating respective page sizes for different translations. A virtual-address cache module manages entries,...
2017/0371798 SYSTEM, METHOD, AND RECORDING MEDIUM FOR COMMON MEMORY PROGRAMMING
A parallel execution method, system, and non-transitory computer readable medium not maintaining a cache coherence, include creating a continuum, the continuum...
2017/0371797 PRE-FETCH MECHANISM FOR COMPRESSED MEMORY LINES IN A PROCESSOR-BASED SYSTEM
Some aspects of the disclosure relate to a pre-fetch mechanism for a cache line compression system that increases RAM capacity and optimizes overflow area...
2017/0371796 EXTRACT TARGET CACHE ATTRIBUTE FACILITY AND INSTRUCTION THEREFOR
A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for...
2017/0371795 Multi-Level System Memory With Near Memory Scrubbing Based On Predicted Far Memory Idle Time
An apparatus is described that includes a memory controller to interface to a multi-level system memory. The memory controller includes least recently used...
2017/0371794 SYSTEM AND METHOD FOR DYNAMIC OPTIMIZATION FOR BURST AND SUSTAINED PERFORMANCE IN SOLID STATE DRIVES
A method and information handling system configured to executing instructions of an SSD dynamic optimization buffer switching system and configured to...
2017/0371793 CACHE WITH COMPRESSED DATA AND TAG
Cache line data and metadata are compressed and stored in first and, optionally, second memory regions, the metadata including an address tag When the...
2017/0371792 PRIORITY-BASED STORAGE AND ACCESS OF COMPRESSED MEMORY LINES IN MEMORY IN A PROCESSOR-BASED SYSTEM
In an aspect, high priority lines are stored starting at an address aligned to a cache line size for instance 64 bytes, and low priority lines are stored in...
2017/0371791 MEMORY CONTROLLER THAT FORCES PREFETCHES IN RESPONSE TO A PRESENT ROW ADDRESS CHANGE TIMING CONSTRAINT
An apparatus having a memory controller is described. The memory controller includes prefetch circuitry to prefetch, from a memory, data having a same row...
2017/0371790 NEXT LINE PREFETCHERS EMPLOYING INITIAL HIGH PREFETCH PREDICTION CONFIDENCE STATES FOR THROTTLING NEXT LINE...
Next line prefetchers employing initial high prefetch prediction confidence states for throttling next line prefetches in processor-based system are disclosed....
2017/0371789 TECHNIQUES FOR MAINTAINING CONSISTENCY BETWEEN ADDRESS TRANSLATIONS IN A DATA PROCESSING SYSTEM
A technique for operating a memory management unit (MMU) of a processor includes the MMU detecting that one or more address translation invalidation requests...
2017/0371788 PROCESSING COMMANDS IN A DIRECTORY-BASED COMPUTER MEMORY MANAGEMENT SYSTEM
A method for processing commands in a directory-based computer memory management system includes receiving a command to perform an operation on data stored in...
2017/0371787 CONTENDED LOCK REQUEST ELISION SCHEME
A system and method for network traffic management between multiple nodes are described. A computing system includes multiple nodes connected to one another....
2017/0371786 SHADOW TAG MEMORY TO MONITOR STATE OF CACHELINES AT DIFFERENT CACHE LEVEL
A processing system includes a plurality of processor cores and a plurality of private caches. Each private cache is associated with a corresponding processor...
2017/0371785 Techniques for Write Commands to a Storage Device
Examples include techniques for a write commands to one or more storage devices coupled with a host computing platform. In some examples, the write commands...
2017/0371784 TARGETED PER-LINE OPERATIONS FOR REMOTE SCOPE PROMOTION
A processing system includes one or more first caches and one or more first lock tables associated with the one or more first caches. The processing system...
2017/0371783 SELF-AWARE, PEER-TO-PEER CACHE TRANSFERS BETWEEN LOCAL, SHARED CACHE MEMORIES IN A MULTI-PROCESSOR SYSTEM
Self-aware, peer-to-peer cache transfers between local, shared cache memories in a multi-processor system is disclosed. A shared cache memory system is...
2017/0371782 VIRTUAL STORAGE
In some examples, techniques for virtual storage includes configuring a single physical storage disk to a virtual storage device that includes a plurality of...
2017/0371781 STORAGE DEVICE AND GARBAGE COLLECTION METHOD THEREOF
A memory controller is for controlling operations of a nonvolatile memory including a first memory block group for storing a first type of data and a second...
2017/0371780 RECONSTRUCT DRIVE FOR DYNAMIC RESIZING
A solid-state drive (SSD) is configured for dynamic resizing. When the SSD approaches the end of its useful life because the over-provisioning amount is...
2017/0371779 METHOD AND APPARATUS FOR REDUCING DATA PROGRAM COMPLETION OVERHEAD IN NAND FLASH
In one embodiment, an apparatus comprises a storage device comprising a NAND flash memory. The storage device is to receive a write request from a computing...
2017/0371778 Reliable Distributed Messaging Using Non-Volatile System Memory
Methods and apparatus for reliable distributed messaging are described. A computer system includes a system memory coupled to one or more processors. The...
2017/0371777 MEMORY CONGESTION AWARE NUMA MANAGEMENT
In a computer system having multiple memory proximity domains including a first memory proximity domain with a first processor and a first memory and a second...
2017/0371776 MIGRATING DATA USING DUAL-PORT NON-VOLATILE DUAL IN-LINE MEMORY MODULES
According to an example, a fabric manager server may migrate data stored in a dual-interface non-volatile dual in-line memory module (NVDIMM) of a memory...
2017/0371775 TECHNOLOGIES FOR BRIDGING GAPS IN EXECUTION TRACES
Technologies for bridging trace gaps include a computing device that traces execution of a program to generate an execution trace and identifies a trace gap in...
2017/0371774 Recording, replaying and modifying an Unstructured Information Management Architecture (UIMA) pipeline
The technique herein substantially improves productivity of Annotator developers by providing methods and systems to develop and test Annotators without having...
2017/0371773 Optimizing Execution Order of System Interval Dependent Test Cases
Systems, methods, and computer-readable media for optimizing the execution order of a set of test programs that includes at least one system interval dependent...
2017/0371772 Test Execution Optimizer For Test Automation
The systems and methods that determine tests that may be executed in parallel during regression testing of an analytics application are provided. Multiple...
2017/0371771 ADAPTIVE TESTING USING DYNAMICALLY DETERMINED SYSTEM RESOURCES OF A COMPUTER SYSTEM
Embodiments include methods, and adaptive testing systems, and computer program products for performing adaptive testing using one or more system resources of...
2017/0371770 AUTOMATICALLY ESTABLISHING SIGNIFICANCE OF STATIC ANALYSIS RESULTS
A static analysis tool configured to determine a significance of static analysis results. The static analysis tool includes computer program code to perform a...
2017/0371769 VIRTUALIZING PRECISE EVENT BASED SAMPLING
A core includes a memory buffer and executes an instruction within a virtual machine. A processor tracer captures trace data and formats the trace data as...
2017/0371768 SYSTEM AND METHOD FOR DETECTING AND ALERTING UNEXPECTED BEHAVIOR OF SOFTWARE APPLICATIONS
A method finding the root cause of errors and/or unexpected behavior of a monitored software application, the method comprising: providing a decision tree...
2017/0371767 DEBUGGING OPTIMIZED CODE USING FAT BINARY
Embodiments of the present invention provide a method, computer program product, and system for debugging optimized code. The system includes a FAT binary,...
2017/0371766 DETERMINATION OF A CULPRIT THREAD AFTER A PHYSICAL CENTRAL PROCESSING UNIT LOCKUP
An automated end-to-end analysis of customer service requests is disclosed. A core dump is received, wherein the core dump corresponds to a customer service...
2017/0371765 AUTOMATED END-TO-END ANALYSIS OF CUSTOMER SERVICE REQUESTS
An automated end-to-end analysis of customer service requests is disclosed. A core dump is received, wherein the core dump corresponds to a customer service...
2017/0371764 FRAMEWORK FOR AUTOMATED GLOBALIZATION ENABLEMENT ON DEVELOPMENT OPERATIONS
Techniques provide a framework for dynamic globalization enablement for an application during software development. A globalization development operation...
2017/0371763 AUTOMATED GLOBALIZATION ENABLEMENT ON DEVELOPMENT OPERATIONS
Techniques are disclosed for providing dynamic globalization enablement for developing an application during software development. A globalization development...
2017/0371762 FRAMEWORK FOR AUTOMATED GLOBALIZATION ENABLEMENT ON DEVELOPMENT OPERATIONS
Techniques provide a framework for dynamic globalization enablement for an application during software development. A globalization development operation...
2017/0371761 REAL-TIME PERFORMANCE TRACKING USING DYNAMIC COMPILATION
Systems, apparatuses, and methods for performing real-time tracking of performance targets using dynamic compilation. A performance target is specified in a...
2017/0371759 INTENT-BASED INTERACTION WITH CLUSTER RESOURCES
Aspects extend to methods, systems, and computer program products for intent-based interactions with cluster resources. One or more computer systems are joined...
2017/0371758 TECHNIQUES FOR ACCURATELY APPRISING A USER OF PROGRESS IN BOOTING A VIRTUAL APPLIANCE
A method, performed by a computing device, includes (a) building a data structure that describes dependence relationships between components of a virtual...
2017/0371757 SYSTEM MONITORING METHOD AND APPARATUS
A system monitoring method and apparatus comprises: collecting periodically status indicator data of a monitored system to generate a status indicator data...
2017/0371756 MONITOR PERIPHERAL DEVICE BASED ON IMPORTED DATA
Various examples described herein provide for monitoring a peripheral device by data imported from the peripheral device. The peripheral data may comprise a...
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